BriteSemi adds 125Msps SAR ADC IP

Brite Semiconductor has released two 12-bit successive-approximation register ADC intellectual-property blocks on a 28nm CMOS process, giving communications SoC developers 1.8V and 2.5V options for high-speed analogue signal acquisition. Both differential designs operate at 125Msps and have completed tape-out verification, functional testing, and performance testing.

The published specifications include an effective number of bits of at least 10.5, spurious-free dynamic range of at least 82.5dB, and total harmonic distortion no worse than -77.2dB. BriteSemi quotes core power consumption of 1.2mW and a core area of 0.07mm² for both voltage variants, with the devices aimed at 5G and 6G RF transceivers, Wi-Fi and Bluetooth baseband circuits, software-defined radios, optical communications, wireless gateways, and communications-oriented edge AI silicon.

The differential input architecture is intended to improve rejection of common-mode interference, an important consideration where a converter sits between an analogue signal chain and digital baseband processing. Noise, distortion, reference stability, clock behaviour, and input settling at the conversion stage all determine how much useful information remains available to the DSP or processor that follows.

A 125Msps SAR converter occupies a useful part of the communications design space. It does not compete with the multi-gigasample converters required for direct conversion of the highest-frequency RF channels, but it can address intermediate-frequency, baseband, and other signal paths where power and silicon area carry greater weight than maximum conversion rate. That balance is particularly relevant when several analogue channels are integrated into the same SoC as processors, interfaces, memory, and digital accelerators.

The choice of 28nm also reflects the economics of mixed-signal design. Analogue circuitry does not scale in the same manner as dense digital logic because capacitor matching, voltage headroom, device noise, and physical isolation impose limits that can make a mature process more attractive than a leading-edge node. A 28nm implementation can still accommodate substantial digital processing while retaining a process environment suited to analogue and RF functions.

BriteSemi’s dual-voltage approach addresses another routine integration problem. Modern digital logic may operate from low core voltages, while analogue circuitry can require greater signal swing or a different supply domain to maintain dynamic range and interface compatibility. Providing qualified 1.8V and 2.5V implementations allows designers to select the converter against an existing power architecture rather than modifying a wider SoC around one fixed analogue supply.

The company says the ADC can also be configured into an I/Q arrangement for communications transceivers. In-phase and quadrature channels are used extensively in RF systems to represent modulated signals, so a matched converter architecture can simplify the handover between analogue frequency conversion and digital baseband processing. The final performance still depends on clock distribution, matching, floorplanning, reference design, and the analogue front end surrounding the IP.

That last point matters because an IP specification is not automatically the specification of the completed chip. Coupling from digital logic, package parasitics, supply noise, PCB implementation, and the behaviour of external amplifiers and filters can all reduce system performance compared with an isolated core measurement. Designers therefore need sufficient characterisation data, integration guidance, and production-test support alongside the headline converter figures.

BriteSemi has positioned the new ADCs inside its broader YouIP catalogue, which includes DDR, SerDes, PCIe, MIPI, USB, memory interfaces, DACs, PLLs, and RF functions. Its business model combines licensable IP with custom ASIC development, allowing the company to participate in both the individual analogue block and its integration into a customer’s completed device.

The completed tape-out and testing work gives the ADCs more substance than a pre-silicon IP announcement, although customer integration remains another stage entirely. Each design still has to be implemented against the target chip’s clocking, power distribution, physical layout, package, application circuit, and manufacturing-test strategy before the published figures can be translated into a production product.

For communications developers, the useful proposition is therefore straightforward: a verified 28nm converter offering 125Msps throughput without demanding excessive core area or power. Whether that balance holds in a completed SoC will depend less on the marketing description of the ADC than on how cleanly its analogue performance survives integration with everything placed around it.