European agencies fund AI-native chip design

SPRIND and the Netherlands’ National Agency for Disruptive Innovation, NADI, have launched a 20-month AI-Native Chip Design Challenge aimed at shortening the path from semiconductor architecture to production-ready implementation. The programme will fund teams developing AI systems that can work across architecture exploration, RTL generation, verification, optimisation, and later stages of chip development.

The challenge is divided into two stages. During the first eight months, selected teams can receive up to €2.6 million each under fixed-price contracts. A second 12-month stage offers up to a further €7 million per team, taking the maximum support to €9.6 million. Applications close on 30 November 2026.

The technical brief extends well beyond generating hardware description code. SPRIND and NADI want teams to develop AI-native systems capable of exploring architectures, creating RTL, checking functionality, and improving power, performance, and area while retaining enough engineering context to move towards manufacturable designs. The agencies identify data security, biotechnology, robotics, and mobility among the application areas of interest.

That breadth reflects a persistent constraint in semiconductor development: improvements at one stage can create additional work elsewhere. RTL that is functionally correct may still produce difficult timing paths, inefficient logic, high switching activity, awkward memory structures, or physical implementation problems. Reducing the time spent writing code has limited value if the design then requires substantially more effort during verification or place and route.

The challenge therefore places weight on autonomous workflows that connect multiple stages rather than treating AI as a standalone code generator. Architecture choices affect data movement, memory access, interface count, and compute structure, while those decisions feed directly into verification complexity, physical implementation, and energy consumption. A system that retains those relationships can test whether an apparent optimisation survives contact with the rest of the design flow.

Commercial EDA vendors are moving in the same direction. Recent full stack design systems already link specification analysis, microarchitecture, RTL generation, verification, debugging, and power, performance, and area optimisation. The SPRIND-NADI programme differs by placing public funding behind teams building AI-native methods and by tying the later phase to production-oriented semiconductor development rather than a software demonstration alone.

Verification remains a hard boundary. Semiconductor sign-off depends on deterministic checks covering functionality, timing, power, physical rules, and reliability. An autonomous system can accelerate exploration and correction, but its output still has to satisfy the same foundry and system requirements as manually developed RTL. Errors introduced early can propagate quickly when more of the flow is automated, making traceability and repeatable checking more important rather than less.

The programme also leaves room for support beyond the two formal stages. SPRIND and NADI say outstanding teams may be considered for follow-on funding in the tens of millions of euros to take designs through tape-out. Terms for that phase have not yet been published, but the inclusion of tape-out separates the programme from challenges that stop at benchmark results or prototype software.

Moving into silicon would expose each system to the parts of the development cycle that are hardest to abstract away: foundry design rules, packaging choices, test strategy, manufacturing variation, and post-silicon validation. It would also provide a clearer measure of whether AI-led design reduces elapsed development time or merely shifts engineering effort between stages.

SPRIND and NADI have scheduled applicant webinars for 9 October and 17 November before the 30 November deadline. The first funded stage will then provide an early test of how much semiconductor design work can be automated while preserving the verification discipline needed for tape-out. The more consequential evidence will come when selected teams attempt to carry those methods through physical implementation and into working silicon.