IN Brief:
- Expedera and Cadence have demonstrated AI workload execution across their combined Origin Evolution NPU and Tensilica NeuroEdge 130 AI Co-Processor in pre-silicon simulation.
- The architecture combines neural network acceleration with programmable preprocessing, postprocessing, and fallback support for operations outside the NPU's capabilities.
- The companies have demonstrated functional integration but have not published combined silicon measurements for throughput, latency, or power consumption.
Expedera and Cadence have demonstrated an integrated artificial intelligence processing subsystem in pre-silicon simulation, combining Expedera's Origin Evolution neural processing unit with the Cadence Tensilica NeuroEdge 130 AI Co-Processor.
The collaboration establishes functional integration between the two semiconductor intellectual property architectures, allowing AI workloads to execute across dedicated neural network acceleration hardware and a programmable processing resource. The companies intend the combination to provide a configurable starting point for systems-on-chip incorporating local inference capabilities.
The demonstration was conducted in a simulated environment before fabrication of a combined semiconductor device. It establishes that the processing blocks can work together under the tested conditions, but does not provide measured silicon performance, manufacturing yield, or power consumption figures for a completed chip.
Neural processing units are designed to accelerate mathematical operations commonly used in artificial intelligence models. These include matrix multiplication, convolution, and other computations that can be distributed across specialised parallel processing structures.
Executing a complete inference workload requires more than performing these calculations. Input information may need to be reorganised or converted before processing, while intermediate results can require operations that are not efficiently implemented within the NPU's dedicated hardware.
Some neural network models also contain functions that the chosen accelerator does not support directly. These operations may need to be executed through programmable hardware, with the resulting data returned to the NPU or transferred to another processing stage.
Expedera's integration addresses these requirements by pairing Origin Evolution with the NeuroEdge 130. The NPU performs supported neural network computations, while the Cadence co-processor assists with preprocessing, postprocessing, and operator fallback.
Operator fallback allows computational functions that cannot be executed directly by the dedicated accelerator to be handled by another compatible processor. This can widen the range of models supported by a semiconductor design without requiring every possible operation to be incorporated into specialised NPU circuitry.
The approach introduces an important architectural consideration: moving data between processing blocks can consume time and energy. A design that accelerates an individual calculation may still encounter bottlenecks when information must be transferred frequently between memory, the NPU, and supporting processors.
Workload partitioning therefore influences the performance of the complete subsystem. The processing resources must be assigned operations that suit their capabilities, while the surrounding software and memory architecture must support the required sequence of calculations.
Origin Evolution uses Expedera's packet-based approach to neural network processing, dividing computational work into smaller units that can be scheduled across its accelerator architecture. The company contrasts this with approaches organised around the execution of complete neural network layers.
This division provides opportunities to manage the execution of different operations, although the resulting efficiency depends on the structure of the model and the available processing resources. The advantages described by Expedera are architectural claims rather than measurements of the newly combined subsystem in fabricated silicon.
Cadence's Tensilica NeuroEdge 130 provides programmable AI processing capabilities intended to complement dedicated neural accelerators. In the combined architecture, it can execute supporting operations and functions that would otherwise require a different processing resource within the system-on-chip.
Programmability is particularly relevant where AI models change after the initial semiconductor architecture has been selected. Software implementations can accommodate some new or modified operations without requiring a dedicated hardware unit to be redesigned for each change.
That flexibility is constrained by the available processor instructions, memory, and computational capacity. An operation executed through programmable hardware may have different latency or energy requirements from one implemented in a dedicated accelerator.
The collaboration allows these trade-offs to be investigated using a common simulated subsystem. Expedera and Cadence report that AI models have executed across the combined architecture, confirming functional interaction between the processing blocks under the demonstrated configuration.
Pre-silicon verification provides an opportunity to investigate interfaces, workload distribution, and software behaviour before committing to semiconductor manufacturing. It can identify architectural problems that would otherwise require changes later in the design cycle.
Physical implementation introduces additional requirements. Circuit timing, memory placement, power distribution, clocking, and the characteristics of the selected fabrication process can influence the performance of a completed device in ways that are not established solely by a functional simulation.
Thermal behaviour and operating voltage also affect real hardware. The measured performance of a manufactured system-on-chip will depend on its implementation and operating conditions, alongside the processing capabilities represented within the development models.
The companies identify applications including industrial edge computing, automotive electronics, smartphones, and data centre systems. These markets have different requirements for processing throughput, available power, memory capacity, and acceptable inference latency.
Industrial vision equipment, for example, may need to prepare camera data before running a neural network, then interpret the model output before passing a result to an industrial controller. The processing sequence can involve operations suited to different hardware resources, while system responsiveness depends on the time required to complete the entire chain.
Automotive implementations can introduce further requirements concerning predictable execution, functional safety, and integration with other electronic control systems. The pre-silicon demonstration does not establish certification of the combined architecture for any particular automotive safety function.
Expedera previously introduced Origin Evolution as a configurable NPU architecture, while Cadence developed NeuroEdge 130 as a programmable processing resource for AI workloads. The latest collaboration concerns their integration rather than the introduction of either processor for the first time.
Both companies intend to support semiconductor designers developing customised inference hardware. Expedera also identifies the use of AI-assisted development processes for adapting its IP to customer requirements, although no quantified reduction in development time has been established for the combined design.
The companies have not identified a customer tapeout, a manufactured device incorporating both blocks, or independent performance benchmarks for the integrated subsystem. Subsequent physical implementations will determine how the demonstrated workload partitioning translates into silicon area, energy consumption, and inference performance.
