Keysight certifies photonic design integration for Tower

Keysight certifies photonic design integration for Tower

Keysight has certified photonic design software for Tower’s PH18 process. The integration brings electronic and optical circuit simulation into a common ADS environment, allowing designers to examine combined behaviour before final foundry verification and fabrication.


IN Brief:

  • Keysight's ADS Photonic Designer has been certified to support Tower Semiconductor's PH18 silicon photonics process design kits.
  • The environment combines electronic and photonic schematic development, simulation, and layout, including electrical-optical-electrical analysis.
  • The PH18 design kit is available now, while final foundry-level verification and tapeout continue to use Tower's tools.

Keysight Technologies has certified its Advanced Design System Photonic Designer software to support Tower Semiconductor's PH18 silicon photonics process design kits, extending electronic circuit design workflows into the development of integrated optical devices.

The certification allows designers to use a common ADS environment for schematic development, simulation, and physical layout involving electronic and photonic components. It builds on more than a decade of collaboration between Keysight and Tower around radiofrequency semiconductor design.

The PH18 process design kit is available now, giving engineers access to photonic component models associated with Tower's manufacturing technology. The integration supports mixed electronic and optical circuit development, while final foundry-level verification and tapeout remain within Tower's own tools.

Silicon photonics uses semiconductor fabrication processes to produce optical components capable of guiding, modulating, routing, or detecting light. These functions can be combined with electronic circuitry in systems where electrical information must be converted into optical signals and subsequently recovered.

Such combinations are used in communications architectures requiring high data throughput. Optical links can carry information between electronic systems, but their performance depends on the interaction between the electronic circuits that generate and receive signals and the photonic devices that transmit them.

An optical transmitter may include an electronic driver connected to a modulator. The driver supplies an electrical waveform, while the modulator changes the properties of an optical signal in response to that waveform.

The resulting transmission depends on both devices. Driver bandwidth, output impedance, signal amplitude, and timing can influence modulation performance, while the electrical characteristics of the modulator affect the load presented to the driver.

At the receiving end, a photodetector converts incoming optical energy into an electrical signal. The surrounding electronic circuitry must process the resulting current or voltage, manage noise, and recover the information encoded in the optical waveform.

Separately evaluating these components can obscure interactions that only become apparent when the complete signal path is considered. Electrical loading, optical losses, device bandwidth, and interconnect behaviour can combine to limit system performance.

These constraints are becoming increasingly demanding as optical links move towards aggregate data rates of 1.6Tbps and beyond. Higher throughput can require multiple high-speed channels, complex modulation arrangements, and careful control of electrical and optical signal integrity.

Historically, electronic and photonic engineers have often relied on different design environments, requiring component data and simulation results to be transferred between tools. Changes to one part of the system may then require repeated model translation or separate analysis before their effects on the remaining circuitry can be assessed.

Keysight's integration provides a route for evaluating photonic components alongside electronic circuits within ADS. The PH18 process design kit supplies physics-based models intended to represent the behaviour of supported photonic structures manufactured using Tower's process.

These models allow optical devices to participate in electrical-optical-electrical simulations. A designer can examine an electrical input, its conversion into an optical signal, transmission through the relevant photonic structures, and the electrical response produced by a receiving circuit.

The analysis depends on the accuracy and scope of the supplied models. Photonic behaviour can be influenced by geometry, optical wavelength, material characteristics, temperature, and the arrangement of neighbouring structures, while electronic behaviour depends on its own device and interconnect parameters.

Combining the models within one environment can help identify interactions earlier in the design process. Changes to a driver circuit can be considered alongside the optical response of a modulator, reducing the need to treat the connected components as independent systems.

The certification extends an established electronic design relationship. Tower's radiofrequency processes have been supported in ADS for more than a decade, including circuit simulation, electromagnetic analysis through RFPro, and electrothermal analysis for relevant silicon germanium amplifier designs.

With PH18 support, photonic circuits can now be developed within the same environment as suitable electronic designs. The arrangement supports co-design across related technologies, although it does not mean that every electronic and photonic component can necessarily be fabricated together using one semiconductor process.

The physical layout workflow includes photonic devices designed to comply with the relevant design rules, together with designer-level layout-versus-schematic checks. These functions can identify certain discrepancies between the intended circuit and its physical representation before the design is submitted for manufacturing.

Design rule checking examines whether the layout meets specified manufacturing constraints, including applicable geometric relationships and permissible structures. Layout-versus-schematic verification checks whether the components and connections represented in the physical design correspond to the intended circuit.

These checks reduce the risk of carrying particular design errors into later stages, but they do not establish that the completed semiconductor will meet every electrical or optical performance requirement. Model accuracy, fabrication variation, packaging, and operating conditions continue to influence the behaviour of the physical device.

Keysight distinguishes its designer-level checking functions from the final foundry verification process. Tower retains responsibility for the manufacturing checks and tapeout procedures required before a completed design can enter fabrication.

The certification is particularly relevant to the development of co-packaged and near-package optics, where optical communications are positioned closer to high-performance electronic processing equipment. Reducing the length of selected electrical connections can address some interconnect constraints, although such architectures introduce requirements involving optical coupling, thermal management, and package assembly.

Power consumption and signal integrity depend on the complete implementation. Shorter electrical paths may reduce certain losses, but photonic devices still require suitable driving and receiving electronics, while packaging and temperature variations can affect optical performance.

The available PH18 design kit allows these interactions to be investigated through supported models before fabrication. Keysight and Tower have not published measured reductions in development cost, design iterations, or system power consumption attributable specifically to the newly certified integration.

Designers can now access the PH18 process design kit through ADS Photonic Designer, combining supported photonic and electronic analysis while retaining Tower's final manufacturing verification process. Subsequent chip implementations will determine how the integrated workflow performs across different circuit architectures and optical communications applications.


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