GlobalFoundries and RAAAM tape out GCRAM test chip

GlobalFoundries and RAAAM Memory Technologies have completed tape-out of a Gain-Cell RAM test vehicle on the foundry’s FDX FD-SOI platform, moving an alternative embedded-memory architecture towards silicon evaluation. The companies say their co-designed GCRAM bitcell can reduce memory area by 40% and memory power by as much as 60% compared with conventional SRAM.

The distinction between tape-out and measured silicon is important. The design has reached the point at which manufacturing data can be released for fabrication, but the announcement does not publish electrical measurements from completed test chips. The area and power figures should therefore be treated as implementation claims to be tested during fabrication, characterisation, and qualification rather than as production-silicon benchmarks.

The collaboration addresses a persistent problem in increasingly memory-heavy SoCs. On-chip SRAM can occupy a large proportion of die area as processors add local buffers for AI, automotive, and data-intensive edge workloads. Moving more data into local memory can reduce expensive off-chip transfers, but increasing SRAM capacity also increases silicon area and contributes leakage and dynamic power.

RAAAM’s Gain-Cell RAM takes a different architectural approach and is intended to remain compatible with standard CMOS manufacturing. GlobalFoundries and RAAAM have co-designed the cell using what they describe as pushed design rules on the FDX process, attempting to increase memory density without adding a specialist memory process that would complicate SoC manufacturing.

The FDX platform provides another useful characteristic through its low-leakage FD-SOI devices. RAAAM says that low leakage can extend GCRAM data retention, which is important because gain-cell memory relies on stored charge rather than the static latch arrangement used by conventional SRAM. Longer retention can reduce the frequency of refresh activity, although the resulting system power depends on the complete memory array, peripheral circuitry, operating temperature, access patterns, and refresh strategy.

The claimed 40% area reduction could have several consequences if it survives silicon qualification. A designer could reduce total die size while retaining a given memory capacity, increase the amount of local memory within the same silicon area, or use the freed space for compute, acceleration, analogue, or interface functions. In applications where memory occupies much of the SoC, even a modest reduction in bitcell area can materially change die economics.

Power reduction has a similarly wider effect. Accessing local memory generally avoids the energy and latency associated with moving data across external interfaces, so increased on-chip capacity can improve system efficiency beyond the intrinsic power consumed by the memory array. That is particularly relevant to edge-AI devices, where repeatedly moving model data and intermediate results between a processor and external memory can dominate the energy budget.

NXP Semiconductors is already evaluating the joint development. Its involvement gives the programme a practical embedded-system context: automotive and intelligent-edge processors have to balance local memory, standby power, functional integration, cost, and long product lifecycles rather than optimise only for the highest possible compute throughput.

The new memory still faces the qualification work expected of any architecture intended to replace SRAM inside a commercial SoC. Designers will need evidence on read and write margins, retention, process variation, temperature behaviour, yield, error characteristics, compiler support, and integration with existing physical-design flows. The practical question is not simply whether an individual GCRAM cell is smaller, but whether a complete usable memory macro retains enough of that advantage once peripheral circuitry and design margins are included.

GlobalFoundries has been broadening the technology surrounding its process platforms, including processor IP, photonics, power, and embedded-memory options. Its recent expansion in photonics and integrated power addresses different system bottlenecks, but follows the same foundry strategy of supplying more of the qualified technology surrounding the manufacturing process rather than leaving customers to assemble every subsystem independently.

Lead customers are expected to receive GCRAM design access from early 2027. That will be the more consequential milestone, because tape-out establishes that the design has entered manufacturing while measured silicon establishes whether its promised density and power advantages survive contact with process variation. Embedded memory is too large a part of many modern SoCs for a credible alternative to SRAM to be ignored, but it is also too fundamental a subsystem for customers to adopt without measured qualification data.