IN Brief:
- Intel and Fortinet will jointly develop the Security Processor 6 ASIC for future network-security systems.
- The project combines Fortinet’s custom architecture with Intel design, packaging, manufacturing, and ecosystem intellectual property.
- Purpose-built processors are absorbing encryption, inspection, networking, and AI workloads within increasingly integrated security appliances.
Intel and Fortinet will co-develop Fortinet’s Security Processor 6, combining a proprietary cybersecurity architecture with Intel’s semiconductor design, packaging, manufacturing, and ecosystem intellectual property.
The companies have not disclosed the processor’s production schedule, process technology, package construction, or performance targets. SP6 will continue Fortinet’s use of purpose-built ASICs to accelerate networking and security functions that would otherwise compete for resources on general-purpose processors.
Fortinet’s existing security processors handle combinations of packet forwarding, traffic inspection, encryption, virtual private networking, application identification, and policy enforcement. Bringing those functions into dedicated silicon allows datapaths, memories, interfaces, and accelerators to be arranged around sustained network workloads rather than a broader computing market.
As traffic volumes rise, security appliances have to maintain throughput while inspecting encrypted sessions, analysing applications, applying threat intelligence, and logging events. Adding each service through software alone can increase latency and reduce forwarding performance, particularly when several functions are enabled across every packet.
Intel will contribute experience in disaggregated semiconductor design and advanced packaging for both AI-enabled and cost-sensitive products. Although the internal form of SP6 remains undisclosed, disaggregation can separate processing, I/O, acceleration, and control functions into optimised blocks, then reconnect them within one package.
Such architectures create choices that conventional monolithic ASICs avoid. Designers can match different functions to suitable process technologies, reuse qualified interface dies, and scale selected elements without rebuilding the complete device, but die-to-die links, power delivery, thermal behaviour, package test, and assembly yield become part of the processor architecture.
Manufacturing and supply assurance form another strand of the agreement, giving Fortinet access to Intel’s fabrication and packaging resources. Network-security equipment commonly remains in production and field support for several years, so controlled silicon revisions and predictable capacity can be as important as peak performance.
The development chain also contains unusually sensitive assets, including cryptographic functions, proprietary datapaths, firmware, verification environments, manufacturing-test content, and provisioning information. Access control, design provenance, secure key handling, and controlled production data must therefore extend from architectural development into assembly, test, and deployment.
European product-security rules are reinforcing that lifecycle approach. Panasonic Industry’s IEC 62443-4-1 certification covers security planning, implementation, verification, updates, and vulnerability handling, illustrating how governance is moving alongside hardware protection as a formal product requirement.
Purpose-built security processors face an inherent tension between efficiency and adaptability. Fixed acceleration can execute established packet-processing and cryptographic functions with lower power and latency, yet threats, protocols, encryption standards, and inspection techniques may change several times during the service life of one appliance.
SP6 will consequently need programmable resources, updateable firmware, and enough uncommitted performance to support services that were not fully defined when the silicon architecture was frozen. Excess flexibility reduces some of the efficiency gained from custom hardware, while excessive specialisation risks leaving the processor unable to absorb new workloads.
Artificial intelligence adds a further layer through behavioural analysis, anomaly detection, classification, and event prioritisation. Those functions require access to useful telemetry and sufficient local compute, but they cannot be allowed to consume the memory bandwidth and processing capacity needed for basic forwarding, encryption, and deterministic policy enforcement.
Advanced packaging may help combine flexible compute with fixed-function acceleration, although continuous operation places severe demands on heat removal and package reliability. A security appliance is expected to maintain rated throughput for long periods, making sustained junction temperature and power integrity more revealing than short peak-performance tests.
Intel gains a named custom-silicon programme as it expands manufacturing activity beyond its own processor catalogue, while Fortinet gains a development route spanning architecture, fabrication, and packaging. The arrangement will be judged when SP6 emerges as qualified hardware with published throughput, power consumption, software flexibility, and long-term availability.
Custom security silicon remains valuable because general-purpose compute cannot absorb every inspection and encryption workload without cost. Its advantage, however, depends on keeping the hardware programmable enough to outlive the threat assumptions made during design, while preserving the efficiency that justified an ASIC in the first place.
