INTERA develops CMOS analogue in-memory computing

INTERA has developed an analogue in-memory computing architecture based on programmable current pulses, using conventional CMOS circuit technology to perform mathematical operations associated with neural-network inference.

The Barcelona semiconductor IP developer is using an architecture called the Programmable Current Pulse Cell (PCPC), which represents numerical values through electrical current and pulse duration. Multiple cells can operate in parallel, with their resulting charge contributions combined to perform vector–matrix multiplication.

INTERA outlined the technology on 3 November 2026, identifying embedded AI, robotics, and larger processing systems among the potential application areas. The company has not published independently verified silicon performance figures or established a commercial production timetable for a complete accelerator based on the architecture.

Neural-network inference requires repeated mathematical operations involving input data and stored model parameters. In many architectures, multiplication and accumulation account for a substantial proportion of the computational workload, particularly within layers containing large arrays of weights.

Conventional digital processing systems execute these operations using arithmetic hardware supplied with data from registers, caches, or other memory structures. The movement of information between storage and computing resources consumes energy and can restrict throughput when the rate of data transfer does not match the available processing capacity.

This constraint becomes more significant as additional arithmetic units are introduced. Increasing the number of processing elements provides limited benefit if the memory system cannot deliver operands at the required rate or accommodate the resulting data transfers.

In-memory computing addresses part of this problem by performing selected calculations within, or close to, the circuitry associated with stored information. The approach aims to reduce unnecessary transfers between separate memory and processing blocks.

INTERA’s design uses analogue electrical behaviour to implement multiplication. Each Programmable Current Pulse Cell generates a current whose amplitude represents a neural-network weight, while the duration of the applied pulse represents the corresponding input value.

The electrical charge delivered by a current over a defined interval is proportional to current multiplied by time. By controlling those two quantities, the cell can produce an analogue representation of a multiplication operation.

The charge contributions from multiple cells can then be accumulated within an array, providing a means of combining several weighted inputs into a common output. This corresponds to the multiply-and-accumulate operation used throughout many neural-network architectures.

INTERA refers to the approach as In-Memory Analog Computing, or IMAC. Its technical description identifies parallel vector–matrix multiplication as a central capability, with the Programmable Current Pulse Cell providing the elementary computing function.

The architecture differs from analogue computing approaches that rely on resistive memory devices. Some in-memory accelerators use resistive random-access memory or memristor structures to represent weights through different electrical conductance states.

In those implementations, applying voltages across programmed devices produces currents that can be combined to perform analogue calculations. However, the electrical characteristics of individual cells can vary, and programmed states may change with temperature, time, or repeated operation.

Device variability, conductance drift, programming endurance, and the stability of multiple analogue states are among the engineering challenges associated with those technologies. Their practical significance depends on the memory device, circuit architecture, and accuracy required by the application.

INTERA’s approach instead uses an active CMOS circuit element to generate programmable current pulses. The company is positioning this as a route towards analogue computation using established semiconductor manufacturing processes rather than requiring additional emerging resistive memory materials.

Compatibility with conventional CMOS does not, by itself, establish that the design can be manufactured at an acceptable cost or yield. The circuit must still satisfy requirements involving transistor matching, voltage variation, temperature behaviour, silicon area, power consumption, and testability.

Analogue computing also introduces numerical accuracy considerations that differ from those of digital arithmetic. Electrical noise, current-source mismatch, timing variation, leakage, and parasitic capacitance can influence the charge accumulated during a calculation.

These effects may cause the electrical result to differ from the intended mathematical value. The acceptable error depends on the neural-network model, numerical representation, and the sensitivity of the application to variations in individual calculations.

Some inference workloads can tolerate reduced numerical precision, particularly where models have been trained or adapted for quantised execution. Others require tighter control of arithmetic error, making calibration, circuit design, and numerical characterisation important.

The complete accelerator must also exchange information with conventional digital circuitry. Model parameters and input data are normally prepared in digital formats, while control software and surrounding processors require results that can be interpreted and used by the wider system.

Analogue-to-digital conversion, weight programming, control logic, and calibration circuits can therefore contribute to the area, energy consumption, and latency of the final design. Any efficiency advantage must be evaluated across the complete accelerator rather than inferred solely from the multiplication mechanism of an individual cell.

INTERA identifies artificial neural networks, convolutional neural networks, and spiking neural networks among the model families potentially supported by the architecture.

These workloads do not all have the same computational structure. Convolutional networks repeatedly apply filters to incoming data, while spiking networks use events and their timing as part of the information being processed.

Hardware efficiency will depend on how each network is mapped onto the available array, the precision required, and the amount of supporting data movement. An analogue computing element may be suitable for particular mathematical operations without providing the complete functionality required by every neural-network layer.

The IMAC development also sits alongside INTERA’s separate EAGLE Cognit semiconductor IP. EAGLE uses a digital near-memory acceleration architecture, while IMAC relies on analogue current and charge operations.

The two approaches address related data movement constraints through different circuit mechanisms. EAGLE’s configurable processing resources and software toolchain should therefore not be confused with measured capabilities of the proposed analogue design.

INTERA identifies industrial sensing, robotics, autonomous systems, and embedded AI among the prospective applications. These markets place different demands on processing latency, energy consumption, memory capacity, software compatibility, and the numerical reliability of the completed system.

Battery-powered devices may prioritise average energy consumption, while larger accelerator systems require sustained throughput and efficient interaction with memory. In both cases, total system behaviour depends on more than the electrical efficiency of the individual computing cell.

The company has not disclosed a completed IMAC chip, manufacturing process node, tested silicon area, energy efficiency benchmark, or independently measured comparison with conventional digital accelerators.

Those results will be necessary to establish how the architecture performs under representative operating conditions, including the overhead of data conversion, control circuitry, and memory access.

The current development establishes INTERA’s proposed circuit mechanism and its intended application to parallel neural-network calculations. Silicon implementation and system-level testing will determine whether the design can deliver practical efficiency advantages within commercially manufactured AI processors.