IN Brief:
- Microchip has introduced XpressConnect PCIe 6.0 and CXL 3.1 retimers for AI infrastructure.
- The devices support 64GT/s links, sub-12ns pin-to-pin latency, and flexible link bifurcation.
- Signal integrity and latency are becoming critical limits in dense GPU and memory-disaggregated systems.
Microchip Technology has released XpressConnect PCIe 6.0 and CXL 3.1 retimers for AI data-centre systems, targeting signal-integrity and latency constraints in high-bandwidth accelerator fabrics.
The devices are designed to extend signal reach beyond conventional PCIe Gen 5 and Gen 6 electrical limits, allowing more flexible routing across complex baseboards, riser cards, and cabled interconnects. At PCIe 6.0 speeds of 64GT/s, channel reach and signal quality become major constraints, particularly where dense GPU clusters and memory resources are spread across large server platforms.
XpressConnect retimers support PCIe 6.0 and CXL 3.1, with pin-to-pin latency below 12ns. The devices also support flexible link bifurcation configurations, including 1×16, 2×8, and 4×4, giving system designers more options when routing high-speed links across accelerator, memory, storage, and expansion architectures.
Brian McCarson, corporate vice president and general manager of Microchip’s data centre solutions business unit, said: “AI data centers are increasingly constrained not by compute, but by the ability to move data efficiently across the system. As PCIe 6.0 pushes speeds to 64 GT/s, signal reach and latency become critical design challenges.”
The retimers are designed to work alongside Microchip’s 3nm Switchtec PCIe Gen 6 switches, Adaptec SmartRAID controllers, host bus adapters, and Flashtec NVMe controllers. That wider fabric portfolio gives Microchip coverage across switching, storage, controller, and retimer functions in AI and high-performance computing platforms.
Through Microchip’s ChipLink diagnostic ecosystem, the devices gain access to debug, diagnostics, configuration, and analysis through a graphical interface. ChipLink connects through in-band PCIe or sideband signals such as UART, TWI, and EJTAG, while the retimers support real-time 2D eye capture and PAM4 telemetry for link-health inspection during bring-up, validation, and deployment.
Microchip’s recent product activity has spanned several layers of the electronics stack. Its dsPIC33CK Value Line digital signal controllers addressed cost-sensitive real-time control, while its 3.3kV SiC modules targeted medium-voltage power conversion. XpressConnect sits in a different part of the system, but follows the same shift toward validated component families that cover more of the architecture around the chip.
AI data centres are exposing limits that standard server designs could once absorb more gradually. Memory expansion, accelerator-to-accelerator traffic, storage access, and CXL-based resource disaggregation all increase the number of high-speed links that have to work across longer or more complex physical routes. PAM4 signalling increases bandwidth, while narrowing noise margins and making channel behaviour harder to manage.
Retimers sit between electrical design and platform economics. They do not add compute capacity, but they help determine how far compute, memory, and storage resources can be separated without wasting accelerator time on data stalls. As AI clusters become denser and more disaggregated, the interconnect layer is becoming one of the decisive parts of system performance.
