PICMG updates COM-HPC carrier board design guidance

PICMG has updated its COM-HPC Carrier Design Guide to Revision 2.3, providing additional implementation guidance for the printed circuit boards used to integrate high-performance computer-on-modules into embedded systems.

The 173-page document addresses PCI Express 6.0, camera connectivity, power management, and interface compatibility, reflecting changes introduced through COM-HPC Base Specification Revision 1.3. German embedded computing manufacturer congatec, a participant in the standard's development, confirmed its support for the revised guide on 12 November 2026.

COM-HPC separates the principal computing hardware from the application-specific electronics surrounding it. A computer-on-module integrates the processor, memory, and supporting circuitry, while the carrier board provides external connections, peripheral interfaces, power distribution, and mechanical integration.

The arrangement can extend the useful life of an embedded system by allowing the computing module to be replaced as processing requirements change. Compatibility nevertheless depends on the electrical interfaces and optional features implemented by the module, as well as the physical connection between the two boards.

Revision 2.3 builds on earlier guidance for COM-HPC Client and Mini systems, with particular attention to high-speed connections. Although the updated Base Specification retains existing pin assignments, the introduction of additional interface options does not mean that every module supports the same functions.

PCIe 6.0 presents one of the more demanding implementation changes. The interface uses four-level pulse amplitude modulation, known as PAM4, to increase data throughput compared with PCIe 5.0 without doubling the underlying signal frequency.

PAM4 represents information using four signal amplitudes instead of two. The closer spacing between those levels reduces the available noise margin, making the connection more sensitive to insertion loss, reflections, crosstalk, and other sources of signal degradation.

The physical connection between the processor and a peripheral must therefore be considered as a complete transmission path. Part of its electrical loss budget is consumed within the computing module, leaving a more restricted allowance for traces, connectors, and components on the carrier board.

PCB material selection becomes particularly important under these conditions. Conventional FR4 materials can impose excessive losses over longer connections, while lower-loss laminates may permit greater routing flexibility at additional manufacturing cost.

The design guide provides recommendations for assessing signal paths using different board materials, although the permissible trace length depends on the complete connection. Direct PCIe 6.0 links may require very short routes, with retimers or redrivers becoming necessary where the available electrical budget cannot otherwise be maintained.

Via construction introduces another source of signal degradation. Unused sections of plated through-holes can form stubs that reflect high-frequency energy, making back-drilling or changes to the PCB stack-up relevant when adapting an earlier carrier design for PCIe 6.0.

Reference clock distribution also requires attention. Clock buffers that satisfy earlier PCIe requirements may not provide the jitter performance needed for the newer interface, while connectors and expansion slots must be suitable for the intended operating speed.

These requirements mean that upgrading a carrier for PCIe 6.0 may involve more than changing an interface controller. Board materials, layer arrangement, clock circuitry, connector selection, and the complete routed channel may all need to be reconsidered and validated.

Revision 2.3 also clarifies PCIe lane population and assignment. COM-HPC modules do not necessarily implement every available lane, and gaps within a group may be permitted. A peripheral connected to a lane that is absent on a replacement module may consequently lose its required communication path.

Client and Mini configurations also differ in their preferred link arrangements. Mini implementations can favour an x4 configuration where corresponding Client arrangements use individual x1 links, making the intended module population an important consideration during carrier design.

The guide retains and updates information for adapting Client examples to COM-HPC Mini. Control and sideband signal levels on Mini modules are commonly 1.8 V rather than the 3.3 V associated with corresponding Client implementations, so selected circuits may require different components or voltage translation.

Some high-speed coupling capacitors also occupy different locations in the two arrangements. Connections including PCIe and SATA may require capacitors on the Mini carrier where equivalent Client implementations locate them on the module itself.

Shared pins introduce further configuration limits. A Mini module may allocate particular connections between PCIe, SATA, SGMII, USB4, and display functions according to the capabilities of its processor and supporting circuitry. The final interface selection therefore requires confirmation against the individual module rather than the connector definition alone.

Camera connectivity has been extended through MIPI-CSI C-PHY support alongside existing D-PHY options. C-PHY introduces different electrical signalling requirements, while the complete camera channel must account for the module, connectors, PCB routing, and any attached flexible cable.

The physical arrangement differs between Client and Mini systems. A COM-HPC Mini implementation may locate the camera connector directly on the module, while the Client carrier forms part of the camera signal path. Those distinctions affect the layout and validation work required to support a particular camera configuration.

Revision 2.3 also addresses Modern Standby and PCIe reference clock allocation. Supported devices require suitable clock request and reference clock arrangements to enter independent low-power states, while the module BIOS and associated software must support the intended behaviour.

Modern Standby operation may therefore require coordination with the module supplier before the carrier design is finalised. A hardware arrangement that provides the necessary signals does not guarantee that the required firmware behaviour can be enabled without changes.

Additional clarifications cover USB implementation and the use of interface options introduced through the updated Base Specification. In particular, the COM-HPC connector continues to provide conventional USB 2.0 signalling rather than exposing eUSB2V2 directly, preserving independence from the processor's internal USB implementation.

The document remains a design guide rather than a replacement for the COM-HPC specification. It must be used alongside the Base Specification, the selected module's documentation, relevant component specifications, and the requirements of the intended application.

Before production, the resulting carrier board still requires schematic review, signal integrity assessment, PCB stack-up verification, and mechanical and thermal checks. Prototype measurement remains necessary to establish whether the complete design performs within the required operating limits.

Revision 2.3 provides additional guidance for those implementation decisions as newer computing modules introduce higher-speed interfaces and more flexible peripheral arrangements. The capabilities ultimately available to an embedded system will depend on the specific module, carrier design, and verification results.