IN Brief:
- QuickLogic's enhanced GF 12LP eFPGA architecture can scale beyond 250,000 lookup tables.
- A revised DSP MAC adds a pre-adder, cascade connections, and SIMD functions for signal-processing workloads.
- An optional health monitor detects and corrects SEU-induced configuration-bit errors while the user design remains active.
QuickLogic has expanded its embedded FPGA hard IP for GlobalFoundries’ 12LP process, increasing the supported programmable fabric beyond 250,000 lookup tables while adding a revised DSP block and an optional mechanism for monitoring configuration integrity during operation. The development targets SoCs that require substantial post-manufacturing reconfigurability without moving the programmable logic onto a separate FPGA device.
The architecture builds on QuickLogic’s existing silicon-proven GF 12LP implementation but raises the capacity available to designers. Embedded FPGA places reprogrammable logic inside an ASIC or SoC, allowing selected hardware functions, algorithms, or interfaces to change after fabrication while the remainder of the chip continues to use fixed-function circuitry.
QuickLogic says the enhanced fabric can scale beyond 250,000 LUTs and can be configured with user-defined combinations of lookup tables, BlockRAM, and DSP resources. That flexibility matters because an embedded array does not have to reproduce the broad resource mix required by a general-purpose packaged FPGA. An SoC developer can instead tailor the programmable region around the functions expected to change during the product’s lifetime.
The economic argument remains less forgiving. Programmable logic normally consumes more area and power than a fixed hardware implementation of the same function, so including a larger eFPGA block only makes sense where adaptability carries enough value to justify that overhead. Protocol changes, configurable accelerators, field updates, evolving security requirements, and long-lived aerospace or industrial systems are among the applications where that trade-off can become attractive.
Signal processing receives a more specialised resource in the new architecture. QuickLogic’s revised DSP Multiply-and-Accumulate unit adds an enhanced pre-adder, cascade connections, and SIMD functionality. The company identifies phased-array radar, electronic warfare, satellite communications, wireless infrastructure, and imaging among the intended workloads, all of which can apply repeated arithmetic operations to large streams of sampled data.
Dedicated MAC resources prevent those operations from consuming excessive numbers of general-purpose LUTs. Cascade paths can also make it easier to build wider arithmetic structures, while SIMD operation allows several narrower calculations to share the same resource where the workload permits. The announcement does not publish frequency, throughput, or power figures for the revised block, so its performance cannot yet be compared directly with another FPGA or eFPGA DSP architecture.
The second major addition is an optional Configuration Bit Health Monitor. SRAM-based programmable logic depends on stored configuration bits to define routing and logic behaviour, and energetic particles can create single-event upsets that alter those values. QuickLogic says the monitor can detect and correct configuration-bit errors caused by SEUs while the user’s eFPGA design remains active.
That is a useful capability for high-reliability applications, but it should not be interpreted as making an entire SoC radiation hardened. Configuration integrity is one part of a much larger system problem that can also include memories, state machines, standard-cell logic, clocking, analogue circuitry, power management, package behaviour, and software fault handling. The monitor addresses errors inside the configuration store rather than replacing system-level reliability engineering.
The addition nevertheless fits QuickLogic’s growing exposure to aerospace and defence applications. The company has also been developing large FPGA and radiation-focused programmes around GlobalFoundries 12LP, including test chips and evaluation hardware. Those projects are separate from the new eFPGA release, but they provide a route for process-specific reliability work to feed into a programmable-logic architecture intended for both commercial and high-reliability SoCs.
An embedded implementation also creates different physical-design constraints from a standalone FPGA. A large programmable array has to share power distribution, clocking, floorplan, routing resources, thermal limits, and verification with the fixed portions of the host SoC. Greater capacity therefore brings a larger integration problem as well as more flexibility, particularly where the eFPGA sits close to high-bandwidth interfaces or other compute accelerators.
QuickLogic supports the flow through its Aurora and AuroraPRO tools, covering development from RTL through configuration bitstream generation. Tool integration is central to the value of eFPGA because the programmable block becomes less attractive if designers have to maintain a disconnected implementation flow merely to gain post-silicon adaptability.
The announcement does not provide die-area figures, maximum clock rates, measured power, or a standard availability date for a 250,000-LUT configuration. The tangible changes are therefore architectural rather than benchmark-led: a higher scaling limit, richer DSP capability, and an optional mechanism for maintaining configuration integrity while user logic remains active.
Those changes broaden the range of functions that can be left programmable after tape-out, but the eventual design decision will come down to silicon cost. Flexibility inside an ASIC earns its place when the area and power penalty is smaller than the cost of the redesigns, qualification cycles, or field limitations it prevents. QuickLogic has increased the size of that programmable option; customer implementations will show how often designers can afford to use all of it.
