IN Brief:
- Racyics has fabricated a dedicated test chip for its UCIe PHY on GlobalFoundries’ 22FDX process.
- The PHY supports x16 standard package links at 4 Gbit/s and 8 Gbit/s per pin.
- Integrated functions include transmit and receive paths, clock generation, link training and resistance calibration.
Racyics has brought its Universal Chiplet Interconnect Express physical-layer IP for GlobalFoundries’ 22FDX process onto a dedicated test chip, allowing the die-to-die interface to be characterised under manufactured silicon conditions.
The UCIE_PHY_TC1 test chip implements Racyics’ UCIe PHY and is intended to verify the interaction between its analogue and digital functions before broader qualification. The design supports the UCIe standard package configuration with an x16 data width and operates at 4 Gbit/s or 8 Gbit/s per pin, while transmitter and receiver circuitry, clock generation, link training and resistance calibration are integrated into the hard macro.
UCIe defines a common connection between dies assembled within the same package, separating the physical electrical link from the higher-level protocols carried across it. Chiplet architectures can consequently combine processors, accelerators, memory interfaces and specialist functions that were designed independently or manufactured on different process technologies, provided the physical interface establishes the link, maintains timing and behaves predictably across process, voltage and temperature variation.
Racyics’ implementation connects the UCIe Raw Die-to-Die Interface to the electrical mainband and sideband links. The IP includes an integrated phase-locked loop for clock generation and an APB-connected configuration and status register file, while the physical layout is designed around a 130 µm bump pitch. Those parameters place the interface in the standard package branch of UCIe rather than the finer pitch used by more aggressive advanced packaging configurations.
The PHY has been implemented on GlobalFoundries’ 22FDX platform, an FD-SOI process used where designers require digital logic, analogue capability, low leakage and controllable device characteristics without moving to the smallest available geometry. Racyics positions the interface for consumer and automotive systems, and its published specification includes an Automotive Grade 1 reliability profile with characterisation corners spanning -40°C to 150°C.
Fabricating UCIE_PHY_TC1 allows signal integrity, clock behaviour, transmitter and receiver margins, calibration performance and the interaction between the PHY and package parasitics to be measured directly. Simulation can establish expected behaviour before fabrication, but physical silicon provides the data needed to check whether those models continue to hold once manufacturing variation and real interconnect effects are present.
Racyics’ involvement in the EuroCDP design route has already linked its IP and design capability with efforts to broaden access to European semiconductor development infrastructure. The UCIe test chip advances one specific element of that portfolio from implementation into physical characterisation.
Chiplet interfaces are difficult to correct after assembly because the die-to-die connection becomes part of the packaged device rather than a replaceable board-level link. Electrical margin, training behaviour and interoperability therefore have to be understood before surrounding dies are committed to a production package, particularly where a fault at the interface could leave otherwise functional silicon unusable.
The x16 interface can provide an aggregate raw mainband capacity that scales with the selected per-pin rate, although usable system throughput will also depend on protocol overhead and the wider UCIe implementation. Supporting both 4 Gbit/s and 8 Gbit/s operation gives integrators room to trade bandwidth against power and channel margin rather than forcing every design to operate at the upper rate.
Racyics supplies the PHY as hard macro IP with implementation collateral including layout, timing models, simulation models and integration guidance. Measurements from UCIE_PHY_TC1 can strengthen that deliverable set by replacing assumptions about physical behaviour with characterised data from the 22FDX implementation.
The test chip is a validation milestone rather than a new UCIe specification or a finished chiplet product. Its immediate engineering purpose is to establish whether the physical interface behaves as intended on manufactured 22FDX silicon before system developers treat the PHY as a qualified building block within more complex multi-die designs.
