Dismantled: Q3 2026

Although Q3 2026 produced several concrete milestones, the electronics engineering agenda remained recognisably continuous with the first half of the year. Q2 had already exposed how memory bandwidth, advanced packaging, optical links, power delivery and design automation were becoming harder to separate; from July to September, more of those technologies moved into volume production, deployment planning and regulatory operation.

Semiconductor demand supplied a powerful backdrop, with worldwide sales reaching $146.8bn in July on the Semiconductor Industry Association and World Semiconductor Trade Statistics three-month moving-average measure, 6.4% above June. Growth remained uneven across end markets, however, while AI infrastructure continued to absorb investment in processors, memory, networking, power electronics and semiconductor manufacturing at a rate that increasingly affected the design choices around the compute silicon itself.

Memory provided one of the clearest examples of that dependency. SK hynix confirmed in July that HBM4 mass shipments had begun, advancing a technology cycle already well under way before Q3. Samsung had started commercial HBM4 shipments earlier in 2026, while HBM4E development was already pushing interface speeds and stack capacity beyond the first HBM4 generation. By September, however, HBM was on course to absorb close to 30% of industry DRAM wafer capacity during 2027, compared with roughly 20% currently.

Because HBM and conventional DRAM draw on much of the same wafer capacity, while stacked memory consumes substantial silicon for each usable bit of capacity, accelerator demand can tighten supply well beyond the accelerator market. That pressure had become visible by August, when memory constraints were influencing future HBM configurations as designers examined capacity, availability and validation trade-offs rather than simply specifying the largest possible memory stack.

At package level, the same expansion in AI compute was increasing the difficulty of joining processors and memory together. Advanced packaging was already central to accelerator development before the quarter began, but package area, interposer dimensions, power density and HBM count continued to increase. With conventional large silicon interposers facing practical manufacturing limits, CoWoS-L is expected to take a larger share of advanced AI packaging, using local silicon bridges within a broader redistribution structure as packages move beyond established CoWoS-S dimensions.

Larger multi-die assemblies also carry more demanding thermal, electrical and mechanical interactions, which pushes package engineering more firmly into the wider system design flow. Power delivery can affect timing margin; substrate and redistribution-layer decisions influence signal integrity; thermal expansion introduces warpage and reliability concerns; and increasingly complex assemblies require new approaches to inspection, test access and failure analysis. The package may sit physically between dies and PCB, but its engineering can no longer be treated as an isolated stage between chip design and board design.

That convergence was reflected in design software during Q3, as Cadence extended its existing agentic engineering work into PCB and advanced package development through AuraStack. AI-assisted EDA was already well established, and Cadence had introduced chip-level autonomous agents before the quarter began; AuraStack expanded orchestration across planning, constraints, layout, manufacturability and multiphysics analysis. The resulting PCB and package workflow connects tasks that have traditionally been divided across separate engineering tools and teams.

By the end of September, Synopsys had extended the same trajectory with AgentEngineer and its Autopilot platform for longer-running workflows across verification, implementation, analogue design, manufacturing, simulation and system validation. Autonomous execution increases the amount of engineering work that can be planned, launched and iterated by software, but it does not remove the deterministic parts of the development process. Constraints, physical simulation, design rules, verification coverage and formal sign-off still decide whether an automatically generated result is fit to manufacture.

As those design domains became more interconnected, optical communications continued their own transition from device development towards industrialisation. Silicon photonics and co-packaged optics were established technologies before Q3, with 800G and 1.6T optical products already progressing through the market, but September added more evidence around the production infrastructure required to increase volumes. Tower Semiconductor and NewPhotonics began volume shipments of laser-integrated optical engines supporting 800G and 1.6T connectivity, while Sivers committed $30m to expand its Glasgow indium-phosphide operation towards annual capacity above 100 million continuous-wave DFB lasers.

Device performance continued to advance alongside that manufacturing work, with imec demonstrating a 100GHz germanium-silicon avalanche photodiode on a 300mm silicon photonics platform and net 400Gbps reception at 5V. Yet higher bandwidth alone will not determine adoption as optical links move closer to processors. Laser availability, fibre attachment, optical alignment, bonding, known-good-die strategies, thermal stability and production test all become harder when photonics is integrated more tightly with electronic packages, which is why co-packaged optics process development increasingly spans wafer handling, bonding and nanoimprint technology as well as the optical devices themselves.

Power electronics followed a similar progression from an established architectural direction towards more deployable hardware. Higher-voltage DC distribution for dense AI racks had already been under active development through the first half of 2026, alongside GaN and SiC converters designed for the emerging 800VDC architecture. In August, NVIDIA added an MGX-compatible 800VDC power rack intended for deployment in the second half of the year, allowing existing AC-powered facilities to introduce 800VDC within the row without immediately replacing the building-level electrical architecture.

Semiconductor and infrastructure suppliers filled in more of the surrounding power chain as the quarter progressed. Wolfspeed SiC was qualified for LITEON’s 800VDC platforms, SolarEdge and Infineon developed semiconductor protection capable of microsecond fault isolation, and Infineon devices were selected for Eaton’s medium-voltage solid-state transformer platform by the end of September. Reducing current through higher distribution voltage can lower conductor requirements and some conversion losses, but the architecture also raises the engineering burden around insulation, switching, fault protection, auxiliary supplies, energy storage and safe maintenance.

Beyond AI infrastructure, the quarter’s manufacturing investment showed how semiconductor capacity requirements continue to spread across very different process technologies. Infineon opened its €5bn Dresden Smart Power Fab in July for power semiconductor and analogue/mixed-signal production, Intel committed another €5bn to Leixlip for Intel 3 production, and the Vanguard International Semiconductor and NXP joint venture opened its Singapore 300mm fab in September ahead of planned volume production in early 2027.

VSMC’s 40nm to 130nm process range sits far behind leading-edge logic in feature size, yet the devices produced on those nodes remain fundamental to automotive, industrial, analogue, mixed-signal and power-management systems. Capacity strategy is consequently developing on several fronts at once, with advanced logic, DRAM, power devices, mature-node analogue products, photonics and advanced packaging each demanding different equipment, materials, skills and qualification cycles.

Custom silicon continued to bind many of those technologies together. Hyperscalers have been developing application-specific processors for years, but the surrounding design ecosystem became more structured during Q3 as MediaTek expanded its work around NVIDIA’s NVLink Fusion platform. Bespoke compute is being connected more tightly with HBM, chip-to-chip links, package design and rack-scale networking, making the economic case for a custom accelerator dependent on far more than whether an individual workload can benefit from specialised compute.

Regulation added another engineering dependency from 11 September, when reporting requirements under the EU Cyber Resilience Act began applying to actively exploited vulnerabilities and severe security incidents involving products with digital elements. Full CRA product requirements take effect later, but manufacturers can now face an early-warning requirement within 24 hours of becoming aware of a relevant incident, followed by more detailed reporting within 72 hours.

Longstanding secure-development practices therefore gained an immediate operational component, because firmware provenance, vulnerability intake, product identification, escalation routes and update mechanisms have to remain usable after equipment enters the field. Secure boot, signed firmware and hardware roots of trust address parts of that problem, while controller suppliers have also been adapting their wider security processes to support reporting and lifecycle obligations.

By the end of September, several constraints that had dominated electronics discussion earlier in 2026 were appearing in more concrete forms: HBM was taking a greater share of DRAM manufacturing, optical components were scaling towards higher production volumes, 800VDC had acquired a route into existing facilities, and autonomous engineering tools were spanning more of the design workflow. A faster processor can still be limited by memory, packaging, connectivity, power, verification or post-sale security, leaving those interfaces increasingly central to the performance and viability of the finished system.

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What were Q3 2026’s biggest electronics design stories?

Agentic engineering widened across the design stack

Cadence extended agentic automation into PCB and advanced package development with AuraStack in July, while Synopsys ended the quarter with AgentEngineer and its Autopilot platform for longer workflows spanning verification, implementation, analogue design, manufacturing and simulation. Neither development marked the arrival of AI in EDA: machine learning and workflow automation were already established, and autonomous chip-design agents had appeared before Q3. During the quarter, however, orchestration spread across more engineering domains as chiplets, HBM, package routing, board design, signal integrity and thermal behaviour became more tightly linked. Deterministic verification, physical simulation and sign-off remain necessary, leaving the emerging model closer to supervised autonomous engineering than unconstrained machine-generated hardware design.

HBM4 production intensified the memory capacity squeeze

SK hynix began mass shipments of HBM4 during Q3 as AI accelerator demand continued to consume more advanced DRAM capacity. Samsung had already started commercial HBM4 shipments earlier in 2026, while HBM4E development featured heavily during Q2, so the technology itself was not new to the quarter. More significant was the increasing visibility of its manufacturing consequences. HBM was expected by September to account for close to 30% of industry DRAM wafer capacity during 2027, compared with roughly 20% currently, while supply and validation pressure was already influencing future accelerator memory configurations. Memory bandwidth is now increasingly bound to wafer allocation, package design, thermal limits and conventional DRAM availability.

800VDC gained a route into existing data centres

NVIDIA added an MGX-compatible 800VDC power rack in August, creating a transitional architecture for existing AC-powered facilities ahead of more extensive native-DC infrastructure. Higher-voltage rack distribution, wide-bandgap semiconductors and the future Kyber architecture were already under development before Q3, but the new rack put more detail around how 800VDC could enter operational data centres. Semiconductor and infrastructure suppliers also developed the surrounding conversion and protection layers, including microsecond solid-state fault isolation and SiC-based transformer systems. Higher distribution voltage reduces current at a given power level, while increasing the importance of insulation, switching, protection, energy storage, auxiliary power and maintenance procedures across the rack and row.

Silicon photonics accumulated volume manufacturing evidence

Tower Semiconductor and NewPhotonics began volume shipments of laser-integrated optical engines during September for 800G and 1.6T connectivity, while Sivers announced a $30m expansion intended to take its Glasgow laser manufacturing capacity beyond 100 million devices annually. Optical interconnects and silicon photonics were already central to AI networking before Q3, but the quarter added further evidence of work shifting into manufacturing scale. Imec’s 100GHz Ge/Si avalanche photodiode demonstrated continued device progress, while co-packaged optics process development addressed bonding, wafer handling and photonic-electronic integration. Laser supply, alignment, fibre attachment, thermal stability and production test will increasingly determine how quickly optical links can move closer to compute packages.

Cyber Resilience Act reporting became operational

EU Cyber Resilience Act reporting duties began on 11 September for actively exploited vulnerabilities and severe security incidents affecting products with digital elements. The wider CRA product requirements do not yet apply, so the quarter did not bring the full compliance regime into force; manufacturers can nevertheless now face an early-warning requirement within 24 hours of awareness and more detailed notification within 72 hours. That connects established secure-development practices more directly with post-sale product management. Firmware provenance, vulnerability handling, product identification, signed updates and escalation procedures need to remain usable throughout the supported lifecycle, while semiconductor suppliers have already been adapting internal security processes around the reporting regime ahead of the broader product obligations.

IN answer to…

What changed in electronics engineering during Q3 2026?

Q3 mainly advanced trends already established earlier in 2026. HBM4 entered a further stage of volume production, agentic EDA expanded across more system-design workflows, silicon photonics gained additional volume-manufacturing evidence, and 800VDC acquired a practical transition architecture for existing data centres. EU Cyber Resilience Act vulnerability and incident reporting duties also became operational from 11 September.

Why is HBM affecting the wider memory market?

HBM and conventional DRAM draw on much of the same wafer capacity, while HBM consumes substantial silicon and requires additional stacking, bonding, testing and packaging. Rising HBM production can therefore reduce the capacity available for other DRAM products. HBM is expected to account for close to 30% of industry DRAM wafer capacity during 2027, tightening the connection between AI accelerator demand and wider memory availability.

Why are AI data centres considering 800VDC power distribution?

Higher voltage reduces the current required to deliver a given amount of power, which can reduce conductor requirements and some conversion losses as rack power rises. The architecture also requires suitable converters, solid-state protection, insulation, energy storage and safe maintenance procedures. Q3 added a transitional NVIDIA power rack designed to deliver 800VDC within existing AC-powered facilities.

Is agentic AI replacing electronics design engineers?

Current agentic EDA systems can automate and orchestrate increasingly long sequences of engineering work, but the resulting designs still depend on constraints, physical simulation, deterministic verification, manufacturing rules and formal sign-off. Q3 widened the range of tasks that can be coordinated autonomously without removing the engineering judgement or evidence required before hardware can enter production.