IN Brief:
- TrendForce expects TSMC’s CoWoS-L technology to remain the mainstream advanced-packaging platform for AI chips through 2028.
- Larger accelerator packages are pushing beyond CoWoS-S as designs combine more compute dies and HBM stacks.
- Intel’s EMIB-T offers an alternative bridge-based architecture, although routing density, manufacturing maturity, and production yield remain important differentiators.
TrendForce expects TSMC’s CoWoS-L packaging technology to remain the mainstream option for high-end AI processors through 2028 as growing compute-die counts and HBM capacity push package structures beyond the practical limits of established CoWoS-S implementations.
The shift is being driven by package size. CoWoS-S uses a large silicon interposer beneath compute dies and high-bandwidth memory, providing dense wiring between those elements. That architecture has supported several generations of AI hardware, but increasing numbers of compute chiplets and HBM stacks require a correspondingly larger interposer.
TrendForce says CoWoS-S can accommodate configurations with two SoCs or chiplets and eight HBM modules, and expects the technology to remain in use for some ASICs, including Microsoft’s Maia 200. More expansive accelerator designs increasingly require CoWoS-L, which uses local silicon bridge structures within a broader interposer arrangement rather than relying on one large silicon interposer for the complete package.
The distinction becomes more important as accelerator packages move beyond normal reticle dimensions. Lithography systems expose a limited field area, so very large structures either require stitching or an architecture that avoids making every interconnect layer one monolithic piece of silicon. CoWoS-L places high-density silicon bridges where chip-to-chip and chip-to-HBM connections require them while allowing other parts of the package to use different materials and wiring densities.
NVIDIA and AMD have already adopted CoWoS-L in current AI accelerator programmes, according to TrendForce. Meta’s MTIA 400 also uses the technology, while AWS and Microsoft are expected to introduce CoWoS-L into further internally designed AI processors during 2027.
Demand is rising at the same time. TrendForce expects NVIDIA high-end GPU shipments to increase by about 30% year-on-year during 2026, while AMD is increasing deployment of its MI400 and MI450 families. Hyperscale operators are also developing more internal silicon, extending packaging demand beyond merchant GPUs into custom ASICs.
The resulting pressure is not confined to interconnect density. CoWoS capacity remains constrained, and the larger interposers associated with advanced configurations increase package cost. Those conditions create room for architectures that use local silicon bridges rather than a full large-area silicon interposer.
Intel’s EMIB family is the most prominent alternative. The technology embeds small silicon bridges into the package substrate at the boundaries between adjacent dies, allowing high-density die-to-die connections without placing the entire assembly on a silicon interposer. This can reduce the amount of silicon used in the package, although the surrounding organic substrate still has to carry a substantial proportion of the routing.
EMIB-T extends the approach by adding through-silicon vias to the bridge structure, shortening some signal paths and improving vertical connectivity. TrendForce says Google is expected to adopt EMIB-T in 2027, while AWS is also evaluating EMIB technology.
Routing density, signal integrity, HBM placement, thermal behaviour, assembly yield, substrate design, and access to qualified production capacity all influence the architecture selected for a high-end accelerator. A lower-cost package concept offers little advantage if it cannot achieve the yield or volume required for hyperscale deployments.
Recent redistribution-layer development at Taiyo and imec reflects the same pressure from another direction. Fine-pitch wiring, advanced die placement, and package-scale integration are becoming larger parts of overall semiconductor performance as conventional transistor scaling is supplemented by increasingly complex multi-die systems.
TrendForce currently gives CoWoS-L the advantage on manufacturing maturity and yield, underpinning its forecast that the technology will remain dominant through 2028. Intel’s bridge-based approach nevertheless gives AI processor designers another route as package dimensions, HBM counts, and demand for advanced packaging continue to rise together.
Accelerator vendors can design increasingly large assemblies, but packaging technology still has to turn those designs into high-yielding products at the volumes required by data-centre operators. Over the next two years, production maturity and capacity are likely to determine which packaging architectures move from technical alternatives into sustained volume use.
