IN Brief:
- Weebit Matrix provides a 32 × 32 ReRAM crossbar array containing 1,024 selectable memory cells.
- Evaluation and Quick-Start configurations support electrical characterisation, matrix operations, and FPGA-controlled experiments.
- The research-only platform enables investigation of computational accuracy, latency, energy consumption, and reliability using physical silicon.
Weebit Nano has launched the Weebit Matrix In-Memory Compute Research Program, providing academic and industry researchers with physical resistive RAM hardware for developing and testing computing architectures that perform calculations within memory arrays.
The programme uses a chip containing a 32 × 32 ReRAM crossbar array, allowing researchers to investigate the electrical behaviour of individual memory cells and their use in analogue computation. Weebit is offering two development packages that support different levels of access to the underlying hardware.
The Weebit Matrix IMC Evaluation Package provides direct analogue access for device-level electrical characterisation. The Quick-Start Package adds an integrated development environment, FPGA control hardware, and sample code for system-level experiments involving matrix operations and neural network inference.
Both packages include chip samples, supporting documentation, and hardware incorporating a socket for the memory device. The research chip uses a one-transistor, one-resistor architecture, with 1,024 memory cells arranged across its crossbar structure.
ReRAM stores information through changes in the resistance of a memory element. These resistance states can persist without a continuous electrical supply, providing non-volatile storage that can be integrated into semiconductor designs.
The technology also has analogue characteristics that can be used for computation. Instead of representing information exclusively through binary states, researchers can investigate multiple resistance levels and the current that flows through cells when controlled voltages are applied.
In a crossbar architecture, memory elements are connected through intersecting conductors. Applying electrical signals across the array produces currents determined by the conductance of the selected cells and the voltages applied to them.
Under suitable operating conditions, this behaviour can be used to perform multiply-accumulate operations associated with matrix-vector calculations. Such calculations occur repeatedly in many neural network workloads, particularly during inference.
Conventional processing architectures generally move numerical data between memory and computing units before arithmetic operations are performed. This movement consumes energy and can limit throughput when large amounts of data must be transferred repeatedly.
In-memory computing offers a different arrangement by placing aspects of the calculation within the storage structure itself. Its potential advantage comes from reducing data movement while allowing multiple electrical operations to take place in parallel.
That benefit depends on more than the memory array. The complete system must also generate input signals, measure the resulting currents, convert between analogue and digital representations where required, and coordinate the calculation through supporting control circuitry.
Those additional operations can influence the total energy consumption and latency of the computing system. The degree of improvement therefore depends on the workload, circuit architecture, required numerical accuracy, and the effectiveness of the peripheral electronics.
Weebit’s Evaluation Package allows researchers to examine these characteristics directly. Users can control voltages applied to the array, programme and read individual ReRAM states, and measure how the cells behave under different electrical conditions.
The platform supports investigation of multiple resistance levels, allowing researchers to test how accurately physical memory states can represent values used in a computation. This is an important part of evaluating analogue computing because the electrical properties of real devices do not necessarily correspond perfectly to intended mathematical values.
Cell-to-cell variation, electrical noise, and changes in resistance during operation can introduce errors. Researchers must also consider whether a calculation remains sufficiently accurate when many cells contribute simultaneously to the resulting electrical measurement.
The Quick-Start Package extends the work into a more complete computing environment. Its FPGA subsystem provides digital control and integration functions, allowing researchers to explore matrix-vector operations, neural network inference, and other experimental architectures using the physical array.
Weebit identifies convolution processing and spiking neural networks among the operations and architectures that can be investigated. The availability of those experimental functions does not mean that the hardware has been qualified as a commercial AI accelerator.
The company has previously worked with researchers investigating ReRAM-based computing. A separate evaluation by a US developer of radiation-tolerant AI hardware projected substantially lower power consumption and latency for a particular inference workload compared with a GPU-based implementation.
Those figures were projections derived from an application-specific evaluation. They should not be treated as measured performance guarantees for the newly introduced Matrix development kits or for ReRAM computing in general.
Weebit also identifies radiation tolerance as a characteristic supporting potential research applications in aerospace, defence, and medical electronics. The Matrix platform permits investigation of device behaviour under challenging conditions, including radiation, elevated temperatures, and electromagnetic interference.
The research hardware is not a replacement for qualification of a finished semiconductor component. Reliability testing must establish how the relevant device behaves within its specified electrical, environmental, and operating limits.
Weebit’s published platform information identifies a 128-pin QFN package for the research chip and typical evaluation conditions of 25°C and a 5.5V supply. These specifications provide a reference for experiments rather than a complete operating envelope for a commercial computing product.
Participants can use the platform to compare calculations made with physical ReRAM cells against software simulations and other processing methods. Results may help establish which workloads benefit from in-memory computation and where peripheral overhead, analogue precision, or device variation limits the potential advantage.
Access is restricted to qualified researchers, with applications evaluated against the programme’s research objectives. Weebit states that the platform may be used for research and prototyping only, without commercial use rights.
The company will demonstrate Weebit Matrix at electronica 2026 in Munich from 10 to 13 November. Feedback from participating research organisations is intended to support further development of ReRAM technology and its potential applications in emerging computing architectures.
The programme provides a physical hardware platform for testing questions that cannot be settled through theoretical models alone. Whether ReRAM-based computing progresses towards commercial adoption will depend on measured system performance, reproducibility, manufacturing integration, and the suitability of the technology for individual workloads.
