IN Brief:
- TrendForce expects constrained DRAM supply and uncertain HBM4E validation to affect 2027 processor planning.
- NVIDIA is reported to be evaluating several lower-stack HBM4 and HBM4E options for Rubin Ultra.
- TrendForce forecasts 2027 HBM bit shipments will increase by 50–60% but remain below demand growth.
TrendForce expects constrained DRAM supply to continue through 2027, prompting accelerator developers to evaluate lower-capacity high-bandwidth memory configurations for forthcoming artificial intelligence processors.
The market-research company says NVIDIA has expanded its evaluation of memory options for Rubin Ultra beyond an original 12-high HBM4E design. Alternatives under consideration include eight-high HBM4E, 12-high HBM4, and eight-high HBM4, although the final specification has not been determined.
TrendForce attributes the review to two related constraints: limited DRAM wafer capacity available for HBM production and uncertainty around the qualification schedule and yield ramp for 12-high HBM4E. It also reports that several cloud service providers are assessing lower HBM capacities for internally developed AI accelerators.
The forecast turns memory supply into an architecture decision rather than a late procurement problem. Reducing the number of DRAM layers in each stack can increase the number of stacks or accelerators produced from a constrained wafer supply, but it also reduces memory capacity per processor.
Capacity determines how much model data, activation data, and intermediate state can remain close to the accelerator. A smaller local memory pool may force software to divide workloads across more processors or move data more frequently through the interconnect, increasing latency, energy use, and network traffic.
TrendForce says the principal objective for Rubin Ultra is higher input/output speed. If HBM4E validation and mass production remain on schedule, it expects interface rates of 14–16Gbps, compared with 8–11.7Gbps for the preceding Rubin generation. An optimised HBM4 route may be limited to about 11–12Gbps. These figures are analyst estimates around an unconfirmed product configuration.
Stack height affects more than capacity. Additional layers influence thermal resistance, package thickness, warpage, bonding yield, power delivery, and test complexity. A lower stack may improve manufacturability or thermal behaviour, but the system must compensate for reduced memory capacity and possibly lower aggregate bandwidth.
HBM also competes with conventional products for DRAM wafer starts. Memory suppliers must allocate fabrication capacity between HBM, server modules, mobile memory, graphics products, automotive devices, and industrial components. Advanced packaging capacity and base-die supply add further constraints beyond the DRAM wafer itself.
TrendForce reports that earlier shortages already led cloud providers and server manufacturers to reduce registered-DIMM capacities during the first half of 2026. It also says NVIDIA halved the planned SOCAMM capacity of Vera Rubin Superchip modules because LPDDR5X constraints may persist through 2027.
Those changes illustrate how component availability can reshape a complete platform. Reducing memory may protect a product launch date, but it can alter performance tiers, software optimisation, cooling requirements, rack count, and the economics of a deployed cluster.
Supporting several memory configurations is another option. Multiple stack heights and generations can provide procurement flexibility, but each combination requires signal-integrity validation, thermal modelling, package qualification, firmware support, and performance tuning. Vendors must decide whether the variants can be sold under one accelerator specification or require separate products.
TrendForce forecasts that HBM bit shipments will increase by 50–60% in 2027 while still falling short of demand growth. It expects suppliers to retain pricing power, giving processor developers a second incentive to consider lower-capacity configurations alongside the physical supply constraint.
The final Rubin Ultra design has not been confirmed by NVIDIA, so the alternatives should be treated as supply-chain analysis rather than a product announcement. The broader conclusion is more secure: HBM availability, yield, and cost are influencing processor decisions well before server production begins.
Memory planning now reaches into accelerator architecture, package construction, interconnect design, software partitioning, and data-centre operating cost. A nominal reduction in stack height may preserve shipments, but the consequences extend through the entire system rather than ending at the bill of materials.
