IN Brief:
- SEMIFIVE will take the ASIC from customer specifications through detailed design, packaging, testing, and production.
- LPDDR6, PCIe Gen6, and UCIe-S are planned for the on-device AI architecture.
- The programme targets autonomous equipment processing vision and sensor data where external connectivity is limited.
SEMIFIVE has signed a turnkey development contract with South Korean AI semiconductor company Mobilint for a robotics AI chip under Korea’s K-On-Device AI Semiconductor Technology Development programme.
The project will use SEMIFIVE’s Spec Hand-off development model. Mobilint will define the chip’s principal performance targets and specifications, while SEMIFIVE takes responsibility for detailed semiconductor design, packaging, testing, and the route to mass production.
The planned device will support LPDDR6 memory, PCIe Gen6, and UCIe-S, the standard-package form of the Universal Chiplet Interconnect Express specification. The interface set reflects the amount of data that autonomous systems have to move between cameras, sensors, memory, processing blocks, and external controllers while performing inference locally.
The government programme is intended to connect domestic AI semiconductor developers with companies deploying the resulting technology in specific applications. SEMIFIVE and Mobilint are targeting robotics systems that have to process vision and sensor data in real time, including agricultural machines operating in locations where continuous access to external servers cannot be assumed.
Moving inference onto the machine changes the balance of the semiconductor design. A cloud accelerator can depend on substantial cooling, power, and network infrastructure, while a processor installed on autonomous equipment has to work within tighter electrical, thermal, and mechanical limits. The chip also has to accept sensor data quickly enough for the system to react to changes in its surroundings.
LPDDR6 is intended to provide the memory bandwidth required by those workloads without adopting the power and packaging overhead of larger data-centre memory systems. PCIe Gen6 provides a high-speed route to external devices, while UCIe-S introduces the option of connecting specialised dies or chiplets inside a standard package.
Chiplet partitioning can allow designers to combine functions developed for different roles rather than forcing every element of a processor onto one monolithic die. The trade-offs move into packaging, interconnect latency, power delivery, thermal behaviour, and verification, so the interface only becomes useful when the complete package is engineered as one system.
The contract extends an existing relationship between the two companies. SEMIFIVE previously supported production of Mobilint’s ARIES inference SoC, giving the partners experience of moving an AI design through implementation and manufacturing before beginning the new robotics programme.
It also follows a separate SEMIFIVE custom accelerator programme announced for a North American customer. The new Mobilint project addresses a different operating environment, but both place SEMIFIVE earlier in the development process than a conventional physical-design handoff.
The Spec Hand-off model means architectural choices, interfaces, packaging, and production requirements have to be considered before the detailed implementation is fixed. That becomes increasingly important for AI processors because peak arithmetic performance alone does not determine application performance. Memory movement, sensor input, software support, and the thermal envelope can constrain how much of the available compute is sustained in operation.
Outdoor robotics adds environmental variation to those constraints. Cameras and other sensors have to operate across changing light, temperature, vibration, dust, and movement, while autonomous decision making places predictable latency ahead of maximum benchmark throughput. Local inference can reduce reliance on network connectivity, but the processor and its software then carry more responsibility for maintaining operation when no remote compute resource is available.
SEMIFIVE’s role will continue through packaging, test, and eventual production rather than ending when the design reaches tape-out. Those later stages will determine whether the selected interfaces and compute architecture can be manufactured, qualified, and tested at acceptable yield and cost.
The programme remains at the development-contract stage, with silicon implementation and production still ahead. Its engineering progress will be measured by how effectively the planned memory, chiplet, and high-speed interfaces translate into a device that can sustain robotics workloads within the power and environmental limits of autonomous machinery.
