IN Brief:
- Sheffield is leading CHIMES², a £12.5 million national centre for heterogeneous semiconductor system design.
- The programme will focus on combining multiple chips into faster, smaller, and more energy-efficient electronic systems.
- A national Design Commons is planned to support shared design resources, industry collaboration, and skills development.
The University of Sheffield is leading a new £12.5 million national research centre aimed at one of the harder problems now facing semiconductor development: how to combine multiple chips into compact, high-performance systems as conventional board-level approaches run out of room.
The new Centre for Heterogeneous Integrated MicroElectronic and Semiconductor Systems, or CHIMES², will focus on heterogeneous integration, bringing together different semiconductor technologies in a single system so devices can become smaller, faster, and more energy-efficient without relying on a single monolithic path of scaling. That places the centre squarely in the chiplet and advanced-packaging direction that is becoming increasingly important across compute, communications, automotive, and power-sensitive electronics.
Sheffield is leading the centre with researchers from Cambridge, Oxford, Queen’s University Belfast, Strathclyde, Edinburgh, Newcastle, King’s College London, Manchester, and the Science and Technology Facilities Council, while the University of Southampton will co-develop a national Design Commons. The intention is to create a shared bank of architectures, workflows, and reusable tools that can support industry collaboration as well as hands-on skills development.
The timing is not accidental. The UK’s semiconductor strategy has already identified design, R&D, and compound semiconductors as national strengths, and explicitly flagged heterogeneous integration as an area where the country should build a foothold in future technologies. CHIMES² gives that policy direction a clearer design-led vehicle, with more emphasis on turning academic capability into system-level hardware and reusable design infrastructure rather than leaving value stranded at the IP stage.
