IN Brief:
- Siemens says Veloce proFPGA CS, used with NVIDIA’s chip architecture, has captured trillions of pre-silicon verification cycles in days.
- The platform is aimed at hardware-assisted verification workloads ranging from single-FPGA IP validation to multi-billion-gate chiplet designs.
- As AI and chiplet programmes stretch software, verification, and schedule assumptions, prototype systems are taking on more of the burden before tape-out.
Siemens has pushed its latest Veloce proFPGA CS announcement well beyond the usual benchmark chatter by tying the platform to a verification result that now sits squarely in the scale problem facing AI silicon. Working with NVIDIA, the company said the hardware-assisted verification system has been used to capture trillions of pre-silicon design cycles in a matter of days, a level of workload that conventional simulation and even parts of the emulation flow struggle to support in practical schedules.
Veloce proFPGA CS is positioned as a scalable FPGA-based prototyping system for teams that need more than block-level confidence before first silicon arrives. Siemens says the platform is intended to cover a broad range of tasks, from single-FPGA IP validation to multi-billion-gate chiplet-class designs. That range matters because many current AI and high-performance compute programmes no longer fit neatly into the older design assumption that verification can be divided cleanly between local functional checks and late-stage system integration.
Instead, software stacks, memory behaviour, interconnect complexity, and accelerator interactions increasingly need to be exercised together and for much longer runs. That is where cycle scale starts to matter. Millions of cycles may be enough for basic debug. Billions can reveal much more. But when teams are trying to understand system behaviour under realistic software loads and edge conditions, the verification burden can become vast. If those runs cannot be completed early enough, first silicon risks becoming an expensive validation platform rather than the product milestone it is meant to be.
Siemens is arguing that AI and chiplet-era SoCs have now reached the point where hardware-assisted prototyping must absorb more of that workload. FPGA-based prototypes already had a speed advantage over software simulation, but the latest generation of designs has changed the economics of that advantage. The problem is no longer simply whether a team can prototype. It is whether the prototyping environment scales far enough, debugs cleanly enough, and moves quickly enough to remain useful under the pressure of modern programme schedules.
That pressure is coming from several directions at once. AI silicon programmes are larger, but they are also more software-dependent, which means the hardware must be validated against increasingly mature software environments before tape-out. At the same time, chiplet architectures add packaging and interconnect questions that complicate system-level behaviour. And no one is being given more time. Foundry costs, mask sets, and competitive windows all point in the opposite direction.
Viewed that way, Siemens’ announcement is really about verification infrastructure becoming strategic. The ability to run much longer validation workloads before silicon exists is no longer a nice-to-have for flagship processor projects. It is becoming a differentiator in who can bring complex devices to market without repeated slips or costly respins. That has consequences throughout the design chain, from FPGA capacity and debug software to how teams partition verification tasks between simulation, emulation, and prototyping.
There is also a wider point for engineers outside the very top tier of AI compute. Methods that prove themselves first on frontier SoCs rarely stay there. As tools improve, expectations rise across networking, automotive compute, industrial acceleration, and communications silicon. Better prototyping capability at the high end tends to reset what is considered acceptable elsewhere. Design teams that once treated long software-driven validation as something for hyperscale chip houses increasingly have to plan for similar workflows themselves, even if on a smaller scale.
Siemens has chosen a compelling demonstration partner, but the more important takeaway is structural rather than promotional. Verification is becoming one of the main places where semiconductor competitiveness is won or lost. When cycle counts climb into the trillions before first silicon, the issue is not spectacle. It is a sign that the old balance between architecture ambition and validation capacity is being rewritten again.
