IN Brief:
- Speedata is using Arteris FlexNoC within its Callisto Analytics Processing Unit.
- The on-chip network connects compute engines, memory subsystems, and external interfaces.
- Callisto targets Spark SQL, batch ETL, AI preparation, and agentic analytics workloads.
Speedata has selected Arteris FlexNoC network-on-chip technology for its Callisto Analytics Processing Unit, connecting the processor’s compute engines, memory systems, and external interfaces through a configurable on-chip fabric.
Callisto is designed to execute Apache Spark SQL, batch extract-transform-load operations, AI data preparation, and agentic analytics in purpose-built silicon. The architecture shifts data-processing work away from general-purpose server processors, where large volumes of movement, filtering, joining, and transformation can consume substantial compute and memory bandwidth.
FlexNoC replaces a collection of individual buses with a structured network of links, switches, and interfaces. Different traffic classes can share physical resources while retaining defined priorities, bandwidth allocations, and latency behaviour, and blocks operating at different frequencies or using different protocols can be joined through the same fabric.
As processor designs become more heterogeneous, the interconnect increasingly determines how much of the available compute can be used. Engines remain idle when requests, intermediate results, or input data cannot reach them quickly enough, while over-provisioning every path increases silicon area, power consumption, routing pressure, and verification effort.
Analytics workloads expose that balance particularly clearly because many operations have lower arithmetic intensity than neural-network matrix calculations. A query may scan, select, join, sort, and aggregate large datasets while performing comparatively modest computation on each item, so useful throughput depends heavily on the rate at which information moves between memory and the specialised engines.
AI data preparation produces a similar pattern. Training and inference systems often require information to be decoded, normalised, tokenised, filtered, reformatted, or combined before it reaches an accelerator; when those stages run entirely on host CPUs, they consume power and can leave expensive AI hardware waiting for prepared data.
Dedicated analytics silicon offers a route to separating those functions from the general-purpose compute layer, but adoption will depend on how readily existing frameworks can direct work to the device. Application performance will reflect software integration, query planning, data placement, and transfer overhead as much as the peak capability of the accelerator.
Within the chip, transactions generated by compute engines, memory controllers, host interfaces, and management functions may compete for the same routes. Arbitration must prevent a high-volume stream from creating unacceptable latency elsewhere, while backpressure and buffering have to absorb short-term imbalances without triggering stalls across the device.
Compression can ease the same constraint from another direction. ZeroPoint’s ZeroStream IP compresses lossless data as it passes through processor and accelerator memory paths, increasing the effective bandwidth of an existing interface. Speedata and Arteris are addressing the topology and control of that movement, showing how transport has become an architectural discipline alongside the compute engines themselves.
Physical implementation also benefits from a distributed fabric. Long global buses are difficult to time across a large die, whereas routers and segmented links can divide communication into more manageable paths. The NoC still consumes area and power, but it gives designers greater control over wire placement, clock-domain crossings, and the locations where capacity is most valuable.
Verification remains demanding because the fabric must preserve transaction ordering where required, handle backpressure, avoid deadlock, and maintain coherency assumptions across a large number of possible traffic combinations. Security boundaries and fault behaviour add further work when the same network carries data belonging to different processes or trust domains.
Power management cannot be separated from those functions. Individual accelerator regions may enter lower-power states while other blocks continue operating, requiring the interconnect to manage isolation, retained state, clock gating, and transactions directed towards an unavailable endpoint without corrupting data or locking the system.
Callisto enters a processor market increasingly divided into workload-specific engines linked through software frameworks and high-bandwidth memory systems. GPUs dominate many AI calculations, yet analytics, networking, storage processing, search, and data preparation are attracting separate accelerators because their computational and memory-access patterns differ substantially.
By adopting FlexNoC, Speedata is treating on-chip data movement as a primary part of its analytics architecture rather than a service added after the compute blocks have been chosen. Callisto’s commercial performance will be measured through complete application throughput and operating cost, both of which depend on keeping specialised engines supplied with data without allowing the fabric itself to become the bottleneck.
