IN Brief:
- Synaptics is combining Wi-Fi 7, Bluetooth LE 6.0, Thread/Zigbee, and local AI processing in a single device for smart and industrial edge nodes.
- The SYN765x adds wireless sensing, host-less operation options, and a compact hardware footprint to reduce board space and system complexity.
- Sampling is due in Q2 2026, with production targeted for Q4 as edge AI functions move closer to the radio and further away from the cloud.
Synaptics is pushing further into AIoT integration with the SYN765x, a single-chip device that combines Wi-Fi 7 connectivity, local AI processing, and wireless sensing in a package aimed at battery-powered and space-constrained hardware. The target applications include smart appliances, home automation systems, and industrial IoT nodes, where the usual design trade-off has been between richer connectivity features and the cost, board area, and power penalty of adding more silicon.
The SYN765x integrates Wi-Fi 7, Bluetooth LE 6.0, and Thread/Zigbee across the 2.4GHz, 5GHz, and 6GHz bands, while on-chip acceleration handles predefined AI-native control and signal-processing functions. Synaptics is also giving the part deployment flexibility: it can be used as a co-processor beside a host application processor or MCU, or run in standalone and host-less configurations using its on-chip memory and processing resources. That opens the door to designs that drop a separate microcontroller altogether.
The more interesting angle is that the radios are being positioned as sensing tools as well as connectivity blocks. Synaptics is using Wi-Fi Channel State Information with on-device machine learning for presence detection, motion tracking, and proximity awareness, while Bluetooth Channel Sounding is being pitched as a lower-cost route to accurate ranging than technologies such as mmWave radar or ultra-wideband. That shifts the chip from a wireless companion into something closer to a context engine for edge devices.
From a hardware standpoint, the company is pointing to a tri-band 1×1 20MHz architecture, concurrent Wi-Fi, Bluetooth, and Thread operation, sustained 20Mbps throughput up to 200m, and a PCB footprint below 100mm2. The package uses QFN to avoid the need for non-essential PCB complexity, integrates LNA, PA, and T/R switches, and is being positioned at up to 25% lower RBOM than comparable multi-chip alternatives. The result is a part aimed as much at simplification as at raw feature count.
Sampling is expected to begin in calendar Q2 2026, with production targeted for the last quarter of the year. Development kits are also due in Q2, with Synaptics directing developers toward its Astra Developer Zone as the platform comes to market. The direction of travel is clear enough: more of the edge stack is collapsing into a single device, and connectivity silicon is starting to look a lot more like application silicon.
