IN Brief:
- Dolphin Semiconductor and Perceptia Devices have formed a partnership covering power management, audio, monitoring, and PLL IP.
- The collaboration combines Dolphin’s low-power mixed-signal portfolio with Perceptia’s low-jitter clocking technology.
- The partnership supports demand for pre-integrated IP portfolios as SoC designs become harder to assemble and verify.
Dolphin Semiconductor and Perceptia Devices Australia have formed a strategic collaboration to offer an expanded semiconductor IP portfolio for complex system-on-chip designs.
The partnership combines Dolphin’s IP in power management, high-quality audio, and in-situ monitoring with Perceptia’s phase-locked loop technology. The combined offer covers switching and linear regulators, voltage monitors, low-power oscillators, timing monitors, high-precision delta-sigma converters, audio amplifiers, voice activity detection, and advanced PLL IP.
Perceptia’s PLL technology is designed for low jitter, power efficiency, scalability, and use across multiple process nodes. Dolphin’s portfolio is focused on low-power mixed-signal IP for markets including industrial, high-performance computing, IoT, consumer electronics, and automotive systems.
The collaboration gives chip developers access to complementary IP blocks that are commonly needed together in advanced SoC designs. Clocking, power management, audio, and monitoring may be sourced through separate design decisions, but their behaviour is closely connected once implemented on silicon. Power noise can affect timing performance, timing behaviour can influence converter quality, and on-chip monitoring increasingly feeds safety, reliability, and lifecycle-management functions.
That interdependence is becoming harder to manage as SoCs integrate more analogue, digital, sensing, and control functions. A modern chip may need multiple voltage domains, high-quality clocking, always-on sensing, audio front-end capability, diagnostic monitoring, and power optimisation. Integrating those blocks from disconnected suppliers can increase verification load and expose interface assumptions late in the programme.
Chip development is also moving toward greater use of qualified IP as process costs rise and product cycles shorten. Companies are less willing to design every supporting block internally unless it provides clear differentiation. That has increased demand for silicon-proven IP and supplier ecosystems that reduce integration risk.
The mixed-signal portion of that market carries particular weight because analogue IP is less portable than digital IP. Layout, noise sensitivity, device matching, process variation, and packaging conditions can all influence performance. A PLL that performs well in isolation still has to function in the electrical environment created by regulators, converters, digital switching, and sensor interfaces around it.
In-situ monitoring adds a further layer to the portfolio. Timing monitors and related observability IP are becoming more valuable as SoCs are deployed in safety-related, high-reliability, and long-lifecycle systems. Automotive, industrial, and data-processing devices increasingly need to monitor operating conditions, detect degradation, and support functional safety or predictive-maintenance strategies.
Audio sits within the same integration pattern. Voice interfaces, low-power wake-word detection, industrial acoustic sensing, and consumer audio systems depend on carefully managed analogue and mixed-signal design. Combining audio converters, amplifiers, voice activity detection, low-power clocking, and power IP gives SoC developers a clearer route to always-on functions without inflating power budgets.
The partnership points to a more modular SoC supply chain in which design teams select coherent IP clusters rather than isolated blocks. As semiconductor development becomes more expensive, reliable mixed-signal subsystem assembly from proven IP is becoming a competitive factor across industrial, automotive, IoT, and computing markets.
