Allegro DVT supports European automotive chiplet platform

Allegro DVT is contributing video semiconductor IP to the CHASSIS Automotive Base Die, a European 5nm chiplet platform being developed for software-defined vehicle compute architectures.

The Automotive Base Die is designed as a central integration and communication hub for automotive system-on-chip infrastructure. It will support third-party chiplets through the Universal Chiplet Interconnect Express standard, allowing vehicle processors to be assembled from specialised functional blocks rather than only from monolithic silicon.

Allegro DVT’s role centres on video encoding and decoding IP for automotive video pipelines. The technology supports ADAS cameras, surround-view systems, digital cockpit functions, and in-vehicle infotainment, where high-resolution video streams have to be processed under tight limits on memory bandwidth, latency, and power consumption.

CHASSIS is coordinated by Bosch and funded through the Chips Joint Undertaking and national authorities. BMW, imec, and Bosch are among the organisations involved in the Automotive Base Die programme, which is intended to support an open European chiplet ecosystem for secure and scalable vehicle electronics.

The platform has already drawn specialist IP from several areas of the embedded stack, with graphics processor IP being added to the same automotive chiplet project. Video, graphics, AI, safety, security, and high-speed interconnect are all moving closer together as vehicle architectures shift from distributed ECUs toward zonal and centralised compute.

That shift is changing semiconductor requirements inside the vehicle. Workloads that once sat inside narrow-function controllers are now being consolidated into larger processors that must support perception, graphics, sensor fusion, diagnostics, driver assistance, over-the-air updates, and cybersecurity. Silicon therefore has to scale across vehicle classes without forcing every function into a bespoke die.

Chiplets offer one route through that problem. A base die can provide shared integration, communication, and management functions, while separate chiplets add graphics, AI acceleration, video processing, sensor handling, or security according to the target platform. In principle, that reduces duplication and improves reuse across several model cycles.

The automotive environment, however, leaves little room for casual integration. Die-to-die interoperability, signal integrity, thermal coupling, safety documentation, test coverage, fault isolation, and long-term supply all have to be proven at a level that consumer and datacentre chiplet deployments may not require. UCIe provides a useful foundation, but qualification will still depend on implementation detail.

Video processing is a particularly demanding part of that architecture. Camera count and image resolution are increasing across driver assistance, automated driving, parking, cabin monitoring, mirrors, and cockpit systems. Moving those streams through a central compute platform without excessive memory traffic or latency is a hard design constraint, especially when functional safety and power budgets sit alongside image quality.

Other recent automotive semiconductor work has underlined the same pressure from the physical layer upward, including on-chip EMC protection designed for vehicle electronics. More compute can only be useful if it survives the electrical, thermal, and lifecycle conditions imposed by automotive platforms.

Allegro DVT’s contribution gives the CHASSIS project a specialist video-processing layer inside a broader European attempt to define reusable automotive silicon building blocks. The central test will be whether the platform can combine openness, performance, safety, and supply continuity in a form that vehicle manufacturers can carry across several generations of software-defined electronics.