IN Brief:
- Spanish companies, universities, and research centres are forming partnerships around semiconductor development.
- Projects include RISC-V chiplets, reusable analogue IP, automated transistor sizing, materials, and edge processing.
- Progress will depend on foundry access, qualified design tools, packaging, test, and commercial ownership.
AESEMI and MicroNanoSpain have brought Spanish semiconductor companies, universities, and research organisations together to form new partnerships around processor design, analogue IP, materials, prototyping, and edge computing.
The first MatchMaking Day was held at the Escuela de Organización Industrial in Madrid, where participants presented technologies that could be combined across future commercial and publicly funded programmes. The initiative is intended to connect projects that might otherwise remain isolated within academic, regional, or corporate networks.
Among the largest programmes represented was DARE, a €240m European initiative involving 38 partners and 29 work packages. Its development programme includes a general-purpose RISC-V processor, an AI processing unit, and a vector-processing chiplet for future high-performance and exascale computing systems.
RISC-V provides an open instruction-set architecture around which developers can create processor cores and software without relying entirely on proprietary CPU instruction sets. Commercial competitiveness still depends on the microarchitecture, physical implementation, verification, memory system, interfaces, compilers, operating-system support, security, and manufacturing process surrounding that instruction set.
DARE is developing hardware and software together, since processor capability can be lost when the compiler, runtime, memory hierarchy, or application framework fails to exploit the underlying architecture. Chiplet integration adds further demands around die-to-die interfaces, packaging, test, thermal management, and system-level yield.
Spanish researchers also presented work intended to make analogue and mixed-signal intellectual property easier to reuse. The agnostIP framework separates circuit intent from implementation details tied to a particular process or design tool, while the CMOS Analog Synthesizer automates transistor sizing against defined circuit constraints.
Analogue reuse remains considerably more difficult than digital IP reuse because circuit behaviour depends closely on device models, process variation, layout parasitics, matching, noise, temperature, supply voltage, and physical geometry. A block transferred to another foundry or process node may require substantial redesign even where its functional specification remains unchanged.
Improved abstraction and synthesis could nevertheless reduce repeated engineering work across data converters, sensor interfaces, clocking circuits, power management, and mixed-signal control. The quality of the resulting design will depend on model accuracy, corner analysis, layout automation, verification evidence, and the extent to which the design system exposes its limits.
Further projects covered ultra-pure chemicals used in semiconductor cleaning and etching, rapid prototyping services, FPGA-based perception hardware, and neuromorphic processing for embedded systems. The WETCHEM project is developing European sources of chemicals including hydrofluoric acid, ammonium fluoride, and sulphuric acid, where trace metal contamination can reduce yield in advanced manufacturing.
At the system level, the BEGI prototype uses FPGA processing for four-dimensional perception, combining spatial and temporal data for low-latency vision. Other participants presented event-driven and spiking neural-network technologies intended to reduce energy consumption by processing data only when a relevant event occurs.
These activities connect materials, circuits, processors, design tools, and applications, reflecting the fact that semiconductor policy cannot be built around wafer fabrication alone. A functioning industry also requires process design kits, IP, software, packaging, test, prototyping access, and customers prepared to qualify the resulting hardware.
The appointment of new leadership at European RISC-V platform company Quintauris illustrates the parallel effort to bring greater consistency to processor cores, development tools, software, and compliance methods. Fragmentation across those layers can slow adoption even where the base instruction set remains open.
Spain faces a similar coordination problem across its wider semiconductor base. Universities may produce strong circuit research, while start-ups develop specialist IP and European programmes fund demonstrators, but each project still needs access to tape-out, packaging, test, qualification, sales channels, and customers.
Tool access presents a particular barrier because advanced design and verification systems carry substantial costs before a design reaches silicon. As electronic design revenues continue to rise, smaller companies and research teams need shared infrastructure that allows them to evaluate processes and tools without reproducing a complete commercial design environment internally.
Test-before-invest schemes and university prototyping centres can reduce early financial risk, although they require clear intellectual-property rules, predictable access, technical support, and a defined route from a successful demonstrator into repeatable production. A prototype produced through exceptional support is of limited value when the same route cannot sustain later volumes.
National collaboration must also remain connected to European foundries, packaging specialists, equipment suppliers, and customers. Semiconductor supply chains are too specialised for most countries to recreate every capability domestically, making selective strength and cross-border integration more practical than complete national self-sufficiency.
The Madrid initiative provides a structure for finding complementary technologies, but its progress will be visible through joint tape-outs, licensed IP, qualified materials, funded companies, and products entering customer programmes. Those outcomes require sustained engineering ownership long after the introductory meetings have concluded.
