IN Brief:
- Siemens has agreed to acquire Grenoble-based EDA developer Defacto Technologies.
- Defacto automates SoC creation, connectivity, timing constraints, power intent, and early implementation assessment.
- The acquisition extends Siemens’ design flow from initial RTL assembly through verification and sign-off.
Siemens has agreed to acquire Grenoble-based Defacto Technologies, adding automated system-on-chip creation and integration technology to its electronic design automation portfolio.
Operating at register-transfer level, Defacto’s tools automate SoC assembly, design restructuring, connectivity, timing-constraint generation, and power-intent development. The technology also brings implementation assessment and verification closer to the point at which architects combine processor cores, memories, interfaces, accelerators, security functions, and reusable semiconductor IP.
Financial terms have not been disclosed, and completion remains subject to customary regulatory conditions. Founded in Grenoble in 2003, Defacto has concentrated on the increasingly difficult transition between an SoC’s architectural definition and the implementation work that determines whether it can meet performance, power, area, and schedule targets.
Siemens plans to integrate the acquired technology with its existing semiconductor design environment, extending continuity from initial design creation through downstream implementation, verification, and sign-off. A persistent design model should reduce the manual translations and disconnected representations that accumulate as projects move between architecture, RTL development, synthesis, physical design, and verification.
As SoCs acquire more clock structures, power domains, operating modes, and third-party IP blocks, assembly has become a substantial source of programme risk. A connection that is logically correct at RTL may still create congestion, timing, power-distribution, or floorplanning problems once the design reaches physical implementation, while late architectural changes can disturb several verification environments at once.
Bringing implementation evidence forward allows architects to test assumptions while the design remains comparatively inexpensive to alter. Connectivity can be checked against physical constraints, timing intent can be generated alongside the assembled hierarchy, and power-domain decisions can be reviewed before they become embedded in synthesis scripts and downstream sign-off flows.
Power intent is particularly vulnerable to fragmented toolchains because modern devices may shut down, retain, or voltage-scale different regions independently. Isolation, level shifting, state retention, and control sequencing must remain consistent with the functional design; a mismatch can remain concealed until gate-level verification or physical implementation, when corrections affect more of the programme.
Chiplet-based development adds another layer of dependency, even where individual dies are designed separately. Interfaces, package topology, power delivery, thermal behaviour, test access, and die-to-die timing all influence the suitability of the component architecture, which encourages EDA suppliers to link formerly distinct stages of semiconductor and system development.
That convergence is already visible at board and package level, where Cadence’s AuraStack environment coordinates physical implementation with electrical, thermal, and mechanical analysis. Siemens is strengthening a comparable thread further upstream, where the quality of SoC construction shapes every subsequent implementation and verification task.
Automation does not remove architectural judgement, since reusable IP arrives with different assumptions about resets, clocks, bus protocols, debug access, low-power operation, and physical placement. Its value lies in exposing those assumptions consistently, applying repeatable construction rules, and preserving the relationships between the functional hierarchy and the constraints that accompany it.
Verification capacity is another pressure point. Adding blocks and interfaces expands the number of operating states and corner cases, while each manual modification creates the possibility that one representation no longer matches another. Earlier integrated checks can reduce avoidable rework, although full functional, formal, power-aware, and physical verification remains necessary before sign-off.
The acquisition also adds a European EDA development team while governments and manufacturers are investing heavily in regional semiconductor capacity. Fabrication and packaging plants require commercially viable designs to keep them occupied, and design productivity will determine how effectively Europe converts research programmes and specialist IP into devices that reach volume manufacture.
Once Defacto is integrated, Siemens will span a larger portion of the path from SoC construction to implementation and product engineering. The practical test will be whether engineering teams can move between those stages without rebuilding intent, constraints, and verification context at each hand-off, because complexity is now accumulating as quickly in the design flow as it is in the silicon itself.
