Microsoft deploys AMD Helios across Azure

Microsoft will deploy AMD’s Helios rack-scale computing platform across Azure while adding new virtual-machine families built around sixth-generation EPYC processors for AI data systems, semiconductor design, and technical computing.

Three Azure offerings are planned: HDv2 virtual machines for data processing, HXv2 systems for electronic design automation and high-performance computing, and ND MI455X v7 instances for production-scale AI inference. Helios will provide the rack architecture underpinning the MI455X service.

HDv2 instances will contain nearly 500 physical EPYC processor cores, 4TB of RAM, 32TB of local NVMe storage, and 400Gb Azure Boost networking. The configuration is intended for data preparation, search, reinforcement learning, and agent coordination, where large memory capacity and rapid access to local storage can determine how effectively accelerators elsewhere in the workflow are supplied.

HXv2 is designed around 176 EPYC cores operating at frequencies above 5GHz, accompanied by 50% more addressable cache per core and virtual-machine sizes approaching 2TB or 4TB of RAM. An 800Gb InfiniBand interface supports distributed-memory workloads, including RTL simulation, scientific modelling, and engineering analysis.

The ND MI455X v7 service will use AMD’s Helios rack-scale system for reasoning, search, and agentic inference. Rather than treating the accelerator as an isolated card, the architecture coordinates processors, accelerator memory, networking, switching, cooling, and software across a complete rack.

Cloud infrastructure is becoming more specialised because the workloads surrounding AI differ markedly from one another. Model inference depends on accelerator throughput and memory bandwidth, data preparation favours large CPU and storage resources, and semiconductor simulation often rewards high clock frequency, large caches, substantial memory, and predictable inter-node communication.

Separating those services allows the hardware to be matched more closely to the computational pattern. A GPU-heavy system can be inefficient for a memory-intensive RTL simulation, while a general-purpose CPU instance may spend excessive time preparing or moving data before an accelerator can begin useful work.

Electronic design automation remains one of the more demanding cloud-computing cases because projects contain large databases, many tool stages, and licensing arrangements that do not always scale linearly with added processors. Simulation, place and route, extraction, verification, and multiphysics analysis also respond differently to cache size, memory bandwidth, local storage, and network latency.

The HXv2 design concentrates on single-thread performance and memory alongside distributed capability. Many EDA jobs contain sequential sections or shared-data structures that limit scaling, so adding cores without improving memory access and per-core performance can produce modest gains while raising infrastructure cost.

Cloud deployment offers burst capacity during verification peaks and tape-out schedules, although security, data sovereignty, tool licensing, predictable runtime, and the movement of very large design databases remain practical constraints. Validation against commercial EDA flows will therefore carry more weight than processor specifications considered in isolation.

Data movement presents a comparable limit inside AI systems. Lossless compression within processor and accelerator memory paths is one approach to extracting more useful bandwidth from existing interfaces, while Helios addresses the same pressure at rack scale through coordinated compute and networking.

Microsoft is continuing to combine externally supplied processors with its own silicon and systems, creating a heterogeneous infrastructure fleet rather than standardising on one architecture. That approach provides more options for matching workloads to hardware, but it also increases the engineering required to deliver consistent security, orchestration, monitoring, and software behaviour.

For AMD, the agreement extends its Azure role beyond x86 server processors into a coordinated platform spanning CPUs, accelerators, networking, and the ROCm software environment. Competitive performance in AI infrastructure is increasingly measured at rack and application level, where power delivery, cooling, software maturity, and interconnect efficiency can outweigh the headline capability of an individual chip.

The three services also connect semiconductor development with the computing systems that consume the resulting devices. HXv2 is intended to accelerate the design and verification of future silicon, while Helios and MI455X supply one of the large-scale platforms driving demand for those chips.

Azure deployments beginning in the second half of 2026 will provide a production test of that integrated approach. Throughput, utilisation, software compatibility, and operating cost will show whether specialisation across data preparation, EDA, and inference can deliver more useful work than a broader instance type stretched across all three.