IN Brief:
- Samsung will supply high-bandwidth memory for Broadcom AI accelerator programmes.
- The agreement includes 2nm and future foundry processes alongside 2.3D and 2.5D packaging.
- The companies expect the relationship to generate more than $200 billion in business through 2030.
Samsung Electronics and Broadcom have expanded their semiconductor relationship to include high-bandwidth memory, advanced-node foundry production, and heterogeneous packaging for artificial-intelligence infrastructure.
Next-generation HBM devices will support Broadcom accelerator programmes, while the foundry element covers Samsung’s 2nm and future process technologies. Integration work will use 2.3D and 2.5D packaging, bringing logic, memory, and supporting silicon into increasingly dense assemblies.
The five-year relationship is expected to represent more than $200 billion in memory and foundry business through 2030. Broadcom develops custom accelerators, networking silicon, connectivity devices, and other infrastructure components whose performance now depends on several semiconductor technologies being qualified together.
HBM places several DRAM dies in a vertically stacked structure connected through through-silicon vias. Locating that memory close to an accelerator increases available bandwidth and reduces the energy consumed moving data compared with conventional memory devices mounted further from the processing die.
Large accelerators increasingly exceed the practical cost or yield limits of a single monolithic device, encouraging designers to divide compute, I/O, analogue, networking, and memory functions among several dies. Each can then use a process selected for its density, voltage capability, analogue behaviour, cost, or manufacturing maturity.
Samsung’s 2.3D and 2.5D technologies provide different routes for joining those dies with HBM stacks and package substrates. The selected structure influences interconnect length, routing density, signal integrity, power delivery, thermal resistance, package dimensions, assembly complexity, and production yield.
AI supply has become a system-level constraint
Reserving leading-edge wafer capacity no longer secures a finished accelerator when the same programme also depends on HBM stacks, interposers, substrates, package assembly, high-speed test, and cooling equipment. A delay in any one of those stages can leave otherwise completed logic dies without a route into a saleable device.
Memory supply has already become a wider industrial concern, prompting SEMI to caution against poorly targeted market intervention as governments consider responses to constrained capacity. HBM requires specialised manufacturing and assembly, while demand from AI infrastructure competes for capital and production resources with other memory categories.
Bringing logic manufacturing, memory, and packaging into one commercial framework can reduce coordination risk, although responsibility becomes more concentrated. HBM yield must remain consistent across several stacked dies, advanced logic must achieve acceptable wafer yield, and the assembled package must survive production without introducing mechanical, electrical, or thermal defects.
Testing grows more complicated as integration increases. Known-good dies have to be identified before expensive assembly stages, while completed devices require high-speed electrical tests capable of exposing faults in memory channels, die-to-die links, package routing, and power distribution.
Repair options narrow once several costly dies have been joined. A defect in one component can compromise the value of the complete assembly, making early test coverage, traceability, process control, and supplier coordination central to manufacturing economics.
Thermal behaviour will remain one of the principal design limits, since accelerators and tightly packed memory stacks generate substantial heat within a restricted area. Temperature affects performance, retention, reliability, and operating life, while the package must carry power and high-speed signals through thousands of connections without creating excessive loss or noise.
The collaboration also strengthens the position of suppliers capable of coordinating several stages of semiconductor production. Accelerator developers increasingly need process technology, memory, packaging, and test capacity to advance on compatible schedules rather than converging through separate agreements late in a programme.
Second-source planning will remain difficult because custom accelerators become closely tied to a particular process, memory interface, and package. Operators deploying systems at scale will nevertheless continue to examine geographic exposure, capacity concentration, and the feasibility of migrating future generations between manufacturing partners.
Broadcom and Samsung are planning across several product cycles rather than a single device generation. Production yield, HBM availability, packaging throughput, and the pace of volume deployment will provide the practical measures of whether that coordination produces a more resilient supply chain.
