IN Brief:
- SK hynix recorded quarterly revenue of KRW79.3tn and operating profit of KRW60.5tn.
- Mass production HBM4 shipments began while HBM4E samples reached major customers.
- Capacity, advanced packaging, qualification, and long term contracts continue to shape usable AI memory supply.
SK hynix has begun mass production shipments of HBM4 as demand from AI infrastructure helped the memory manufacturer deliver record second quarter revenue and operating profit. Revenue reached KRW79.3187tn, while operating profit rose to KRW60.5426tn with a 76% operating margin.
Both DRAM and NAND benefited from stronger pricing and a richer product mix, although high bandwidth memory remained the principal growth engine. HBM4 moved from customer qualification and sampling into commercial supply during the quarter, marking the first volume step for an interface that raises bandwidth while increasing the complexity of die stacking, base die integration, thermal control, and package yield.
Sample shipments of HBM4E were also completed during the first half of 2026. The higher performance derivative is intended for future accelerator platforms, where its route into volume production will depend on customer specific qualification, manufacturing maturity, and the availability of advanced packaging capacity.
Beyond HBM, shipments have started for products manufactured on SK hynix’s sixth generation 10nm class, or 1c, DRAM process. Sales of SOCAMM2 modules increased during the quarter as server architectures shifted towards memory configurations designed around dense AI compute rather than conventional enterprise workloads alone.
Production changes are also evident in NAND flash, where 321 layer products now represent the largest share of output. SK hynix expects them to account for about half of its domestic NAND production by the end of the year, alongside rising demand for high capacity enterprise solid state drives that supply datasets, checkpoints, embeddings, and model parameters to training and inference clusters.
Memory capacity moves closer to compute planning
As accelerator throughput rises, the memory hierarchy increasingly determines how much of that compute can be used. Bandwidth governs how rapidly data reaches the processing engines, while attached capacity determines the size of the model and working set that can remain close enough to avoid repeated transfers through slower parts of the system.
HBM addresses the bandwidth problem by placing multiple DRAM dies in a vertical stack connected through dense interconnects. That architecture provides far greater throughput than conventional DIMMs, yet it also concentrates production risk across known good dies, stacking yield, thermal behaviour, substrates, base dies, and the final assembly process.
The second quarter semiconductor market had already drawn memory, foundry capacity, packaging, and equipment investment into the same supply problem. HBM4 shipments now move one part of that transition from roadmaps into manufacturing, where yield and customer acceptance will determine usable volume.
Long term supply agreements give memory manufacturers clearer demand visibility and support capital commitments, but they also reduce flexibility elsewhere in the market. Capacity allocated to major accelerator customers may leave smaller processor developers and server manufacturers with fewer opportunities to secure qualified devices at short notice.
The growth of 1c DRAM and 321 layer NAND shows that the pressure extends well beyond accelerator memory. Training systems need substantial host memory, while storage must sustain repeated movement of large datasets and intermediate results; once one bottleneck is eased, the limit may migrate into the CPU memory channels, storage fabric, network, cooling system, or power architecture.
As interfaces become more tightly coupled to accelerators, HBM4 is less interchangeable than commodity memory. Accelerator suppliers control electrical interfaces, stack configurations, package designs, thermal limits, and qualification procedures, which ties the final memory product closely to a particular compute platform and makes changes after launch more difficult.
SK hynix enters that transition with record financial performance and an established position in high bandwidth memory, although rapid generation changes will test production discipline. HBM4 must reach stable yield while HBM4E is qualified behind it, and both programmes have to expand without disrupting the wider DRAM and NAND portfolio on which complete AI systems still depend.
