IN Brief:
- The open HBF specification defines eight-high and 16-high NAND stacks with capacities up to 512GB.
- Three performance grades span approximately 0.4TB/s to 3.0TB/s through a UCIe processor interface.
- Commercial adoption will require production devices, conformance tests, qualified packaging, and supporting software.
SK hynix and Sandisk have published initial specifications for High Bandwidth Flash, defining capacities up to 512GB and three performance grades spanning approximately 0.4TB/s to 3.0TB/s. The specification has been released through the Open Compute Project as an open framework rather than a proprietary interface controlled by either supplier.
HBF is intended to sit between high-bandwidth memory and conventional solid-state storage. It uses stacked NAND flash to offer substantially more capacity than HBM while moving data faster than established SSD interfaces, creating another tier for model parameters, cached data, and large inference workloads.
The first specification supports eight-high and 16-high NAND stacks and adopts Universal Chiplet Interconnect Express as the processor connection. That choice would allow HBF devices to sit alongside CPUs, GPUs, and other accelerators through an established die-to-die interface rather than a new supplier-specific link.
The document also covers electrical characteristics, package connections, reliability guidance for stacked dies, and software input-output requirements. Those details are essential because a useful memory tier depends on controller behaviour, error handling, thermal limits, packaging yield, and software discovery as much as headline bandwidth.
SK hynix and Sandisk began their formal standardisation partnership in August 2025 and launched the wider consortium in February 2026. Google and Tenstorrent are now participating, bringing cloud, processor, and AI-system interests into a programme that began with two memory suppliers.
Broader adoption will still require controller vendors, packaging providers, and software developers to accept the same assumptions. An open specification reduces the risk of a single-vendor attachment, but interoperability will depend on conformance tests, reference controllers, firmware, and production-qualified packages.
The companies are positioning HBF primarily around AI inference, where model weights and retrieval datasets can exceed the capacity available close to an accelerator. HBM remains the faster, lower-latency resource for active computation, while NAND-based storage offers far greater capacity at lower cost. HBF is intended to narrow that performance gap without presenting flash as a direct replacement for DRAM.
Kim Chun-sung, executive vice-president and head of solution development at SK hynix, said: “Through HBF, SK hynix will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency.” Platform-level testing will determine whether that efficiency survives the additional controller, packaging, and software layers.
The published grades provide useful design targets, but they do not yet amount to a complete shipping-product specification. The announcement does not set out random-access latency, endurance classes, controller architecture, package power, or a timetable for commercial HBF devices, leaving system architects unable to compare the proposal directly with current HBM, CXL-attached memory, or high-end NVMe storage.
Alongside the HBF work, SK hynix has shown its tenth-generation V10 4D NAND, built with 375 active layers. The company says the technology improves performance per watt by 2.5 times compared with its previous generation and plans to begin mass production of high-performance, high-capacity enterprise SSDs using the NAND early in 2027.
The NAND development matters because HBF will depend on dense, energy-efficient flash if it is to sit close to processors without overwhelming thermal and power budgets. Stacking more dies increases capacity, but also raises packaging, heat-removal, and yield challenges.
Flash endurance and write behaviour will also shape the first practical deployments. Inference workloads may read large model files repeatedly, but caching, model updates, and data preparation still generate writes. Controller policy will need to protect the stacked NAND without turning endurance management into another source of latency.
HBF has therefore moved from a supplier concept into an open architectural proposal with credible industrial backing. The next milestones are less glamorous than a terabyte-per-second figure: measured silicon, interoperable controllers, qualified packages, and software capable of moving data between storage, HBF, HBM, and processor caches without creating another bottleneck.
