IN Brief:
- First-generation VDPU ASIC samples have returned from fabrication and are undergoing chip-level characterisation.
- A four-card FPGA implementation delivered up to 5.77 times the vector-search throughput of a dual-socket CPU comparison platform.
- Dnotitia plans ASIC-based evaluation in Q4 2026, while published performance figures currently relate only to the FPGA implementation.
Dnotitia has received first silicon for its Vector Data Processing Unit, moving the dedicated vector-search accelerator from FPGA evaluation into chip-level characterisation ahead of planned ASIC system tests in the fourth quarter.
The first-generation VDPU is designed to offload vector retrieval workloads used in retrieval-augmented generation, semantic search, and agentic AI systems. Instead of accelerating the neural-network arithmetic normally associated with GPUs and AI inference processors, Dnotitia targets the search stage that retrieves relevant vectors from large indexes.
The architecture has already been tested in a four-card FPGA server. In that configuration, Dnotitia recorded up to 5.77 times the vector-search throughput of a dual-socket CPU server running the same software stack while maintaining equal or better recall. The company states explicitly that those measurements relate to the FPGA platform and are not final ASIC performance figures.
Moving from programmable logic into a dedicated chip changes clock frequency, memory behaviour, interface implementation, power consumption, and achievable parallelism. First-silicon characterisation allows basic functionality, timing, electrical behaviour, and production variation to be measured directly rather than inferred from simulation or FPGA emulation.
Dnotitia also reports results from a 4,096-dimensional multimodal-vector workload in which its FPGA implementation reduced host CPU use during index construction by 92% and host-memory consumption by 73%. The design has been tested with FAISS, Milvus, and hnswlib across brute-force KNN, IVF, NSW, and HNSW indexing methods.
Compatibility with established libraries and databases is central to the commercial case for a specialist accelerator. Vector-search infrastructure is already built around widely used software stacks, and a processor that requires applications to adopt a proprietary data model or programming environment would create an additional barrier to deployment. Dnotitia plans wider library and database support as the ASIC platform develops.
The company is targeting ASIC-based system evaluation during Q4 2026 and has set an objective of reaching up to ten times the vector-search performance of a CPU-based server. That remains a target rather than measured silicon performance. Dnotitia has not yet disclosed the process node, clock frequency, on-chip memory, external-memory interface, host interconnect, board power, package, or production schedule.
VDPU differs from the growing class of general AI inference processors. Devices such as Axelera AI’s Europa processor concentrate on neural-network inference and expose metrics around compute throughput, memory bandwidth, power, and server integration. Dnotitia is instead attempting to remove database-style vector retrieval from the host CPU and memory hierarchy.
That workload is expanding as AI systems perform repeated searches rather than a single prompt-and-response transaction. Retrieval-augmented applications may issue several searches to assemble context, while agentic systems can search, inspect results, reformulate a query, and search again. Each iteration creates index traversal and memory traffic that does not necessarily benefit from the arithmetic hardware used for model inference.
A dedicated vector accelerator therefore has to be measured against query throughput at a defined recall level, index-build performance, supported dimensions and index structures, host-resource reduction, data-movement overhead, power consumption, and integration with existing vector databases. The FPGA platform gives Dnotitia an initial set of measurements, but the ASIC must reproduce or improve them under a clearly documented server configuration.
First silicon now allows that validation to begin. Q4 system evaluations should establish whether the dedicated architecture retains its advantage when implemented as an ASIC and whether Dnotitia can provide enough software and system support for vector retrieval to operate as a separate acceleration tier alongside conventional CPUs and AI processors.
