IN Brief:
- X-SRAM is claimed to provide up to five times conventional SRAM density using standard nanosheet CMOS processes.
- NEO says 3D X-DRAM could deliver up to ten times conventional DRAM capacity for future high-bandwidth memory.
- Both technologies remain development-stage concepts requiring measured silicon, manufacturing validation, and software support.
NEO Semiconductor has introduced a memory platform combining its X-SRAM on-chip memory concept with its 3D X-DRAM architecture for future high-bandwidth memory systems. The company is positioning the programme as a response to two separate AI-processor constraints: limited local SRAM capacity and the growing size of external model memory.
X-SRAM is intended to increase the amount of memory integrated directly beside processor logic. NEO claims up to five times the density of conventional SRAM while retaining SRAM-class performance and compatibility with standard nanosheet CMOS processes. Its stated objective is to move typical on-chip memory capacities from hundreds of megabytes towards the 1GB to 2GB range.
Additional local capacity could reduce the number of transfers sent across a package to external memory. AI accelerators repeatedly move weights, activations, and intermediate results between compute blocks and memory, so retaining more working data close to the processing array can reduce traffic, latency, and energy consumption.
SRAM is widely used for processor caches and scratchpad memory because it offers low latency and does not require refresh. Its conventional six-transistor cell is expensive in silicon area, however, and density improvements have become harder as advanced logic processes scale. NEO says its alternative cell architecture addresses that limitation without introducing a separate memory process.
The company has not published a complete X-SRAM data set covering access time, operating voltage, retention margins, error behaviour, compiler support, or silicon-area comparisons across equivalent foundry nodes. The five-times figure should therefore be treated as a company claim rather than a demonstrated production advantage until fabricated devices and measured results are available.
The second part of the platform, 3D X-DRAM, targets memory outside the processor die. NEO proposes using manufacturing techniques derived from three-dimensional NAND to build vertically structured dynamic memory, claiming that the approach could provide up to ten times the capacity of conventional DRAM used in current HBM stacks.
NEO says proof-of-concept validation has been completed, but it has not disclosed a commercial product, qualified process, bandwidth result, thermal profile, or production schedule. Building a dense vertical memory cell is only one part of an HBM replacement: the architecture must also support wide interfaces, predictable latency, high aggregate bandwidth, error correction, packaging yield, and acceptable power when positioned beside high-value accelerators.
Andy Hsu, founder and chief executive of NEO Semiconductor, said: “X-SRAM dramatically expands on-chip memory density, while 3D X-DRAM dramatically increases HBM capacity.” The two concepts address different levels of the memory hierarchy, which broadens the proposal but also increases the number of technical and manufacturing dependencies.
For processor designers, more on-chip memory can improve utilisation by keeping frequently accessed data near arithmetic units. Greater external capacity can allow larger models or datasets to remain attached to an accelerator without repeated transfers from SSDs or host memory. Neither benefit guarantees a faster system unless software can place and move data effectively across the hierarchy.
Compilers, runtime software, cache policies, and model-partitioning tools will determine whether the additional capacity is used productively. A dense memory tier that is invisible to existing programming tools can create another management burden, while an architecture exposed through standard interfaces has a better chance of fitting established processor and package roadmaps.
Manufacturability is the harder test. X-SRAM must show that its claimed density survives foundry design rules, redundancy, repair structures, and production yield. 3D X-DRAM must demonstrate that a NAND-derived vertical process can meet the speed, power, reliability, and thermal expectations of memory placed beside large AI processors.
The programme also needs a credible route through the wider supply chain. Foundry support, controller design, advanced packaging, test methods, and customer qualification will shape the commercial timetable as much as the cell architecture itself. Memory proposals can remain technically interesting for years without becoming viable products if those surrounding capabilities are missing.
NEO.AI is therefore a coordinated development roadmap rather than a finished platform ready for system qualification. The company has identified genuine pressure points in the AI memory hierarchy, but its density and capacity claims will remain provisional until supported by production-representative silicon, measured performance, and a documented path through manufacturing and software ecosystems.
