IN Brief:
- Innolux's Chip-Last HIPoS architecture combines multilayer redistribution layers with an embedded core for heterogeneous integration.
- The platform uses 620 × 670mm panels and supports minimum redistribution-layer line/space dimensions down to 2/2µm.
- Customer qualification is the next step, with mass production targeted for the second half of 2027.
Innolux has unveiled a Chip-Last fan-out panel-level packaging platform for high-density heterogeneous integration, extending its move from display-panel manufacturing into semiconductor packaging. The architecture combines multilayer redistribution layers with an embedded core under the company’s Heterogeneous Integration Panel on Substrate, or HIPoS, platform and is being positioned for AI and high-performance computing devices.
The process uses 620 × 670mm panels and supports minimum redistribution-layer line and space dimensions down to 2/2µm. Innolux is now targeting customer qualification, with mass production expected in the second half of 2027. Those figures give the programme a more concrete manufacturing target than a generic announcement of packaging capability.
Fan-out packaging creates redistribution structures beyond the original die footprint, allowing several devices and high-density interfaces to be integrated without relying on a conventional package substrate in the same way as established flip-chip architectures. Moving the process from circular wafers to rectangular panels can increase the usable processing area, particularly as AI packages become physically larger, but the format also magnifies challenges in warpage, alignment, deposition, lithography, and process uniformity.
Innolux enters that problem with a manufacturing background unusual for a semiconductor packaging supplier. Its display factories already handle large substrates through repeated thin-film, lithography, inspection, and precision-alignment operations. The company is repurposing parts of that large-area manufacturing expertise for packaging rather than treating the move as an entirely separate greenfield process.
The Chip-Last route expands an existing portfolio that includes Chip-First packaging and through-glass-via technologies. In a Chip-Last sequence, redistribution and supporting structures can be prepared before known-good dies are attached later in the flow. That can reduce the risk of committing expensive processors, chiplets, or memory devices to a package before earlier manufacturing stages have successfully completed.
HIPoS combines multilayer RDL with an embedded-core structure and is intended to support package architectures resembling large heterogeneous integration substrates. Fine 2/2µm routing is important because increasing overall package dimensions does not reduce local interconnect density around processors and chiplets. AI and HPC assemblies instead tend to increase both dimensions at once: the package gets larger while the routing around its constituent dies becomes finer.
The 620 × 670mm format also creates an economic argument. Larger rectangular substrates can potentially process more package area in each manufacturing cycle and reduce the unused edge area associated with round wafers. Those advantages only matter if yield, overlay, and dimensional stability remain controlled across the full panel. A larger substrate that produces more defective assemblies scales cost rather than productivity.
Testing is therefore part of Innolux’s wider FOPLP proposition, although its currently quantified production system belongs to the established Chip-First process rather than the new Chip-Last platform. That separate panel test system can handle as many as 64 devices simultaneously, with Innolux reporting a 50% to 80% improvement in test efficiency through reduced probe movement and indexing time. It also includes ESD protection and multi-temperature-zone capability.
Keeping those two developments separate matters because proven test throughput on Chip-First packages is not evidence that the new Chip-Last process has reached the same production maturity. What it does demonstrate is that Innolux is building packaging and test capability as a connected manufacturing chain rather than treating panel fabrication as the only process that needs to scale.
The company is also offering services spanning wafer chip probing, assembly, and final testing. Advanced packaging increasingly behaves as a manufacturing system rather than an isolated back-end step: known-good-die strategy, redistribution yield, placement, thermal behaviour, inspection, and electrical test all influence the economics of combining several expensive dies in one assembly.
Existing TFT infrastructure could shorten part of the expansion if it can be converted economically. Large-panel handling, process control, and factory automation provide useful starting points, but semiconductor packaging still requires its own contamination controls, materials, dimensional tolerances, traceability, and reliability qualification. Display manufacturing experience reduces some engineering unknowns without removing the package-specific ones.
The wider equipment sector is moving in the same direction. Nordson recently expanded its Vantage platform for panel-level packaging, adding thermal control, alignment, height sensing, and inspection to manage the warpage and local variation that become more troublesome as substrate dimensions increase. Innolux approaches the same manufacturing constraint from the substrate and integration side.
Customer qualification will now determine whether the new platform progresses from process capability into repeatable production. Innolux has set a second-half 2027 mass-production target, leaving the intervening period for package qualification, yield improvement, and ecosystem development. The 620 × 670mm panel and 2/2µm RDL figures establish an ambitious process window; the harder task is maintaining both across production volumes carrying increasingly expensive AI and HPC silicon.
