IN Brief:
- Samsung plans to introduce ASML High-NA EUV into future DRAM high-volume manufacturing by 2028.
- The company is joining industry work on a 12-inch photomask format alongside the established 6-inch platform.
- Samsung expects the larger masks to reduce stitching constraints and improve High-NA manufacturing productivity.
Samsung Electronics and ASML have expanded their semiconductor-manufacturing collaboration around High-NA EUV lithography, with Samsung planning to introduce the 0.55-NA platform into future DRAM high-volume manufacturing by 2028. Samsung is also joining industry development of a larger 12-inch photomask format intended to reduce some of the field-size and stitching constraints associated with High-NA exposure.
The DRAM commitment provides a specific manufacturing timetable for the technology. Samsung says it plans to use ASML High-NA EUV in high-volume memory production for the first time in the industry by 2028, with improved resolution expected to support further DRAM scaling and simplify some process steps.
High-NA EUV increases numerical aperture from the 0.33 used by current production EUV tools to 0.55. The optical change increases resolution, but the anamorphic projection system reduces the exposure field when paired with the industry’s established mask format, introducing design and manufacturing choices around field size and stitching.
Samsung will consequently participate in an industry initiative developing a 12-inch photomask platform. Semiconductor manufacturing has relied on the 6-inch format for decades, and Samsung says a larger mask could increase fab productivity, reduce chipmaking costs, and remove stitching constraints in future High-NA processes.
Those benefits remain development objectives rather than demonstrated production results. A new mask format also requires supporting infrastructure around mask manufacture, inspection, handling, automation, and standards, so adoption depends on a wider supplier ecosystem rather than a change inside the lithography scanner alone.
The announcement also gives Samsung’s High-NA roadmap a second production dimension. Earlier reporting linked High-NA insertion to Samsung’s 1nm-class foundry roadmap around 2030, while the new announcement sets a formal 2028 objective for DRAM high-volume manufacturing.
The two timings are not contradictory because memory and logic place different demands on patterning. DRAM uses highly repetitive structures and is produced at enormous volume, while leading-edge logic includes a wider variety of layout geometries and die sizes. High-NA can therefore be introduced on different layers and at different stages in the two manufacturing flows.
Cost will remain part of the insertion decision. A higher-resolution exposure can replace more complex multi-patterning on some layers, reducing the number of lithography and etch steps, but that saving has to be balanced against scanner cost, process maturity, resist performance, mask infrastructure, throughput, overlay, and yield.
That makes selective adoption more likely than an immediate replacement of conventional EUV. Existing 0.33-NA systems are already deployed at scale, and mature multi-patterning flows can remain economically attractive where their additional process steps cost less than inserting a newer exposure platform.
Samsung’s involvement in both DRAM manufacturing and the 12-inch mask initiative therefore links the scanner roadmap to two practical constraints: when memory production gains enough from the additional resolution, and whether the wider mask ecosystem can remove some of High-NA’s exposure-field restrictions. The 2028 target gives materials, mask, metrology, and equipment suppliers a defined memory-production horizon against which that supporting infrastructure can be qualified.
