IN Brief:
- ACI Enterprise spans specification analysis, microarchitecture, RTL generation, verification, debugging, and power-performance-area optimisation.
- Cognichip says the platform is being used across more than 40 engagements, including work involving Renesas and SiTime.
- The system is designed to keep proprietary semiconductor design information within controlled enterprise environments.
Cognichip has launched ACI Enterprise, extending its semiconductor-specific artificial intelligence platform across specification analysis, microarchitecture, RTL development, functional verification, debugging, and power-performance-area optimisation. The company says Renesas and SiTime are among semiconductor businesses using the technology.
The scope distinguishes ACI Enterprise from AI assistants aimed at an isolated part of the design process. Cognichip is attempting to retain design context as a project moves from written requirements into architecture, synthesizable logic, verification, and implementation targets, allowing engineering decisions made at one stage to remain visible to later parts of the workflow.
That is a harder problem than generating RTL from a prompt. Semiconductor design is constrained by functional correctness, timing, power, area, process technology, interfaces, clocking, test requirements, and verification evidence. Code that appears plausible still has to survive simulation, formal analysis, synthesis, implementation, and ultimately physical silicon.
Cognichip describes its underlying models as physics-informed and purpose-built for semiconductor engineering rather than general-purpose language models attached to existing design tools. The company combines those models with curated semiconductor data and domain-specific workflows intended to connect generated results to measurable engineering constraints.
ACI Enterprise is designed to analyse specifications, assist microarchitecture, generate and verify RTL, accelerate debugging, and explore power, performance, and area trade-offs. Specifications, tests, constraints, implementation data, and generated design information remain connected so engineers can trace decisions rather than treating each AI interaction as an isolated exchange.
Cognichip says the commercial platform is active across more than 40 engagements. Its launch material identifies Renesas and SiTime as adopters, with use cases extending from specification analysis and IP development to digital portions of mixed-signal integrated circuits.
The company has also published aggressive productivity figures. One example describes a single engineer taking a 55-page specification through microarchitecture, RTL, functional verification, and PPA optimisation within several days, compared with what Cognichip says could conventionally require a front-end team for several months.
Such comparisons need careful treatment. Chip projects vary enormously in reused IP, interface count, architecture, safety requirements, analogue content, verification coverage, and process target. A bounded digital design cannot be used to establish a general productivity multiplier for an SoC containing analogue interfaces, complex memories, firmware dependencies, and qualification requirements.
The engineering opportunity is nevertheless substantial even without accepting a universal speed-up figure. Specification checking, repetitive RTL creation, test generation, regression analysis, debugging, constraint handling, and design-space exploration consume significant engineering time. Automating some of that work could change where experienced designers spend their effort without removing responsibility for architectural decisions or final sign-off.
Verification is particularly important. Hardware cannot be patched with the same freedom as application software once masks have been committed and devices manufactured. An AI system that creates RTL faster but also increases the burden of proving it correct merely moves effort from one stage to another.
Security creates a separate barrier to adoption. Semiconductor design databases contain unreleased architectures, customer IP, process assumptions, verification environments, constraints, and product roadmaps. Companies therefore need controls over where prompts, source files, generated code, and model interactions are stored and whether proprietary information can leave their infrastructure.
Cognichip positions ACI Enterprise as an enterprise-controlled system with protections around design-data visibility and deployment. That is likely to matter as much as model performance for larger semiconductor organisations, where legal and customer restrictions can prevent sensitive design information from being submitted to externally trained public AI services.
The platform also encounters clear technical boundaries. Digital design is only part of many devices. Analogue behaviour, RF, signal integrity, clock quality, package parasitics, thermal effects, device matching, and mixed-signal verification remain specialist engineering problems that do not collapse neatly into an RTL-generation workflow.
Cognichip has raised more than $93 million, including a $60 million Series A announced in April, giving it capital to develop both the underlying models and the enterprise software around them. The commercial launch now shifts attention from the concept of semiconductor-specific AI towards repeatability across real customer programmes.
AI is already entering EDA through optimisation, verification assistance, code generation, and design-space exploration. The more consequential question is whether those capabilities can be connected across the design chain without weakening determinism, security, verification discipline, or engineering accountability.
ACI Enterprise is an ambitious attempt to build that connection. Its strongest evidence will not be a generated block or a headline productivity figure, but working silicon produced by teams that can show the design was faster to create while remaining no harder to understand, verify, qualify, and maintain.
