IN Brief:
- EUCLYD has secured more than €200 million in Series A financing led by Samsung, Somerset Capital Partners, Scaleup Europe Fund, and Innovation Industries.
- Its craftwerk architecture combines programmable ASIC compute with custom memory, advanced packaging, and rack-level system design.
- Funding will expand engineering and move the architecture towards physical silicon, measured workloads, and commercial deployment.
EUCLYD has secured more than €200 million in Series A financing to accelerate development of an AI infrastructure platform built around programmable ASIC compute, processor-memory co-design, advanced packaging, and rack-scale systems. The Eindhoven company says the funding will expand engineering, advance its silicon and systems roadmap, strengthen ecosystem partnerships, and prepare the architecture for commercial deployment.
The round is co-led by Samsung, Somerset Capital Partners, the EQT-managed Scaleup Europe Fund, and Innovation Industries. EIFO, imec.xpand, Brabant Development Agency, and Quadri also participated. Peter Wennink, former president and chief executive of ASML, has joined EUCLYD as chairman, bringing semiconductor manufacturing experience to a programme attempting to optimise compute, memory, packaging, and system architecture together.
EUCLYD centres the platform on its craftwerk silicon and Craftwerk Station CWS 32 system. The design combines programmable ASIC processing with a custom memory subsystem and system-level optimisation aimed at reducing the energy and data-movement penalties associated with large inference workloads. Rather than treating the accelerator as an isolated component, the company is developing the processor and surrounding memory hierarchy as one architecture.
Published specifications for each craftwerk system-in-package include 16,384 128-way SIMD processors, up to 8 PFLOPS at FP16 or 32 PFLOPS at FP4, 1TB of memory, and aggregate memory bandwidth of 8,000TB/s. EUCLYD plans to use advanced 2.5D and 3D integration and specifies a nominal power envelope of about 3kW for the package. These remain company targets pending production silicon and independent workload measurements.
At rack scale, the CWS 32 design combines 32 craftwerk packages with 16 CPUs. EUCLYD specifies 1.024 exaflops at FP4, 32TB of memory, 256PB/s of aggregate memory bandwidth, and a power envelope of about 125kW. The figures show where the engineering effort is concentrated: keeping more model data close to the compute resource and reducing dependence on repeated movement through slower external memory paths.
Memory capacity and bandwidth have become limiting factors across AI infrastructure as model size, context length, and concurrent inference demand increase. Recent AI accelerator pricing pressure has also shown how memory supply can influence the cost and availability of complete systems. EUCLYD is pursuing a different memory architecture, but it will face the same requirement to turn headline capacity and bandwidth into sustained application performance.
The engineering challenge extends well beyond arithmetic throughput. Programmable compute requires a compiler and runtime capable of mapping useful workloads efficiently, while advanced packaging has to meet yield, signal-integrity, thermal, and serviceability requirements. Rack deployment adds power delivery, liquid cooling, networking, security, software orchestration, and fault management to the processor design problem.
The memory design also has to be judged against the economics of the complete rack. Very high local bandwidth can reduce time spent moving model data, but the benefit has to justify custom memory, advanced packaging, and cooling complexity. Capacity that cannot be addressed efficiently by the compiler or kept sufficiently utilised may add cost and power without producing a proportional throughput gain. The eventual system therefore has to be evaluated as a balance of silicon utilisation, memory efficiency, thermal density, and cost per inference rather than as a collection of peak specifications.
The financing gives EUCLYD the resources to move through those stages without relying on a single silicon milestone. Its investor group also connects the company to semiconductor manufacturing, European scale-up capital, and system deployment expertise, which may prove as important as the processor architecture once prototypes have to become repeatable products.
EUCLYD now has to convert its published specifications into physical silicon and measured workloads. Compiler maturity, memory behaviour under sustained inference, packaging yield, cooling requirements, and rack-level reliability will provide a clearer test of the processor-memory approach than peak arithmetic figures alone. The Series A round gives the company the capital to attempt that transition at a scale unusual for an early European semiconductor programme.
