IN Brief:
- MACOM's front-end platform reaches 3.2T aggregate throughput using eight 448Gbps PAM-4 channels.
- New quad transimpedance amplifiers and a high-speed PIN photodiode form the receive side of the platform.
- The new receiver components operate alongside MACOM's previously introduced 448Gbps PAM-4 optical drivers.
MACOM Technology Solutions has introduced an optical front-end chipset capable of 3.2T aggregate throughput, using eight 448Gbps PAM-4 channels for next-generation AI, cloud, and high-speed networking links.
The platform combines new high-performance transimpedance amplifiers and photodiodes on the receive side with MACOM’s previously introduced 448Gbps PAM-4 optical drivers on the transmit side. The result is a set of electronic and optoelectronic building blocks intended for module designers developing the next generation of very-high-capacity optical interfaces.
The 3.2T figure is the aggregate throughput across eight channels rather than the speed of a single serial connection. Each lane operates at 448Gbps using four-level pulse-amplitude modulation, increasing the amount of information carried per symbol compared with a two-level NRZ signal.
PAM-4 raises throughput without requiring a proportional increase in symbol rate, but the four amplitude levels sit closer together and leave less noise margin. Bandwidth, linearity, timing, channel loss, and equalisation therefore become increasingly important as the lane rate rises.
The receiver front end has to preserve those reduced signal margins from the optical detector into the electrical signal chain. A photodiode converts incoming light into current, after which the transimpedance amplifier produces a voltage suitable for further processing. Parasitic capacitance, package inductance, detector response, amplifier noise, and frequency response all contribute to the resulting eye opening.
MACOM’s new receiver components are designed to operate at the bandwidth required by 448Gbps PAM-4 links, alongside transmit drivers already developed for the same lane rate. Offering both sides of the analogue front end gives module designers a more closely matched component set, although the finished transceiver still requires lasers or modulators, DSP functions, packaging, fibre coupling, thermal management, and control electronics.
At these data rates, packaging is inseparable from the semiconductor specification. A device measured successfully on a controlled evaluation fixture can behave differently once wire bonds, bumps, substrate traces, connectors, and optical components are added around it.
Short interconnects and tightly controlled impedance therefore become essential. Package parasitics that are insignificant at lower frequencies can consume a meaningful part of the available signal budget when analogue bandwidth approaches the limits required by a 448Gbps channel.
The move towards higher lane rates also reduces the number of parallel channels needed for a given aggregate bandwidth. An eight-lane 3.2T interface avoids doubling lane count compared with a design using slower optical channels, reducing the number of optical and electrical paths that have to be routed through the module.
The trade-off is much greater difficulty on each lane. Modulator bandwidth, photodiode response, driver linearity, TIA noise, DSP equalisation, and manufacturing tolerances all have to be controlled more tightly, while power consumption per channel has to remain low enough for the finished module to be cooled.
That constraint is becoming more important as AI systems increase network bandwidth. Accelerator clusters depend on rapid data movement between processors and switches, so optical connectivity is being pushed towards higher aggregate capacity without allowing module power to rise at the same rate.
A front-end chipset alone does not solve that system problem, but it defines the analogue performance available at the optical boundary. The quality of the final link will depend on how the MACOM devices are combined with the optical source, detector, DSP, package, board, and fibre interface.
MACOM says the chipset solution is available now. The immediate engineering significance is the availability of transmit and receive components designed around 448Gbps PAM-4 lanes, giving optical-module developers hardware with which to begin building and qualifying eight-channel 3.2T links rather than waiting for the analogue front end to catch up with the bandwidth roadmap.
