IN Brief:
- Kioxia is joining Applied Materials’ EPIC Center as an innovation partner for next-generation memory development.
- Joint R&D will cover memory structures, multi-chip stacking, advanced packaging, and materials engineering.
- Applied expects capital spending on the Silicon Valley EPIC Center to scale to approximately $5 billion as customer projects commence.
Applied Materials and Kioxia are expanding their semiconductor research relationship through a new collaboration at Applied’s EPIC Center in Silicon Valley, covering memory structures, multi-chip stacking, advanced packaging, and materials engineering.
Kioxia is joining the centre as an innovation partner, placing engineers from the flash memory manufacturer alongside Applied teams working on semiconductor process and equipment development. The programme is intended to address increasing memory density and performance requirements while keeping new structures compatible with high-volume manufacturing.
The companies have identified four main development areas: advanced memory cells and structures, multi-chip stacking, advanced packaging for stacked memory, and materials engineering. The programme therefore reaches from the physical memory device through to the package and interconnect structures used to combine several dies.
Kioxia’s core manufacturing base is NAND flash, where density improvements increasingly depend on three-dimensional structures containing large numbers of vertically stacked memory layers. Adding further layers increases capacity, but also places greater demands on etch depth, profile control, film deposition, stress management, bonding, and defect control across the wafer.
The interaction between those processes becomes more difficult as the structures grow taller and more complex. An etch process can affect subsequent deposition uniformity, surface conditions can influence bonding quality, and small dimensional variations can be repeated across large memory arrays. Developing one process step without accounting for those interactions can make later integration slower or reduce final yield.
Applied is building the EPIC Center around a more collaborative development model. Semiconductor manufacturers, equipment suppliers, chip designers, universities, and other partners are intended to work on connected process problems within the same secure R&D environment before transferring qualified technologies into production.
The facility is expected to be operationally ready during 2026. Applied says capital spending will scale over time to approximately $5 billion as customer projects begin, making the centre a substantial addition to its existing process-development infrastructure.
Memory development is well suited to this approach because scaling now reaches beyond the dimensions of an individual memory cell. Stacking several chips can increase capacity within a limited package area, but the resulting device requires reliable bonding, short electrical interconnects, controlled thermal behaviour, and manufacturing processes capable of aligning several dies or wafers accurately.
Advanced packaging therefore forms a separate workstream within the Applied and Kioxia programme. The companies plan to investigate integration and interconnect technologies for stacked memory devices rather than treating package assembly as a process that begins only after the memory wafer has been completed.
That direction reflects the increasing use of heterogeneous integration across computing hardware. Logic, memory, accelerators, and interface functions are being combined more closely to increase bandwidth and reduce the distance that data travels between devices, while the semiconductor manufacturing steps needed to build those systems become more closely linked to package assembly.
Kioxia brings experience from high-volume flash manufacturing, while Applied contributes equipment and process technologies spanning deposition, etch, materials modification, metrology, and other semiconductor manufacturing stages. The partnership gives both companies access to a common environment in which changes to device structure can be evaluated alongside the processes needed to manufacture them.
The programme does not identify a specific future Kioxia product, memory generation, process node, layer count, or production start date. The announcement establishes a development framework rather than introducing a finished device, and no performance target has been disclosed for the memory structures that will result from the work.
Materials engineering will be central to any later implementation. Higher-density structures can require films with different electrical, mechanical, and thermal properties, while new bonding and interconnect schemes place additional demands on surface quality and material compatibility. A process that improves one parameter can introduce stress, resistance, contamination, or reliability problems elsewhere in the structure.
Applied’s EPIC model is intended to expose those interactions earlier in development. Kioxia engineers can evaluate memory concepts alongside process equipment and materials work rather than waiting for individual tools to reach a later development stage before integration begins.
The collaboration also expands the customer ecosystem forming around the new Silicon Valley centre. Applied has been adding semiconductor manufacturers and research partners ahead of full operation, building a programme in which process technology is developed against specific device requirements rather than only through equipment suppliers’ internal roadmaps.
Kioxia’s programme now adds next-generation memory to that work. The first measurable outputs will be process results and integration methods rather than a new product announcement, with commercial significance depending on whether the joint research can move from experimental structures into repeatable memory and packaging processes suitable for high-volume manufacturing.
