IN Brief:
- e²LEAD brings together 14 German and Dutch partners across automotive, semiconductor, packaging and research disciplines.
- Development covers chiplet packaging, high performance data links, thermal interfaces and Smart Power System integration.
- Reliability work combines physical testing with digital twin methods for package design and validation.
The European e²LEAD project has brought chiplet integration, power delivery, thermal interfaces, test methods and digital twin engineering into an automotive supercomputing demonstrator.
Led by Robert Bosch, the German and Dutch consortium includes 14 industrial and research partners spanning vehicle manufacturers, semiconductor companies, packaging specialists and universities. The programme has received the 2026 Xecs Innovation Award after work on hardware intended for increasingly centralised vehicle computing architectures.
Three technical areas underpin the programme: high performance data communication and thermal interfacing; automotive chiplet packaging and Smart Power System integration; and reliability and safety using new test methods alongside digital twin design. Each area addresses a constraint that appears when processing functions are concentrated into fewer, more capable compute modules.
Chiplet architectures divide processing, memory, interface or specialist functions across separate dies before reconnecting them inside a package or module. Different functions can use semiconductor processes suited to their own electrical requirements, but that choice moves more responsibility into the package because data, power and heat must cross the boundaries between dies without undermining system performance.
Die to die links require controlled impedance, predictable signal integrity and low loss interconnect as data rates rise. Power delivery has to support high current at low processor voltages, while heat must move through a package containing several active devices and materials with different thermal and mechanical behaviour. A change that improves one path can increase stress elsewhere, so electrical, thermal and mechanical design cannot be separated cleanly.
Automotive qualification adds vibration, temperature cycling, long service life and functional safety requirements to that package design. Repeated heating and cooling can strain solder joints, substrates, interposers and die attach materials because each layer expands at a different rate. Local power density also creates temperature gradients that are not visible from an average package temperature alone.
e²LEAD’s Smart Power System work places power conversion alongside the compute package rather than treating it as a distant board function. Vehicle distribution voltages remain much higher than processor core voltages, so the final conversion stages carry large currents and become sensitive to resistance, inductance and switching losses. Shorter delivery paths can reduce those parasitic effects, but they also place additional heat close to already dense compute silicon.
Digital twin models allow the consortium to test some of those interactions before physical hardware reaches later validation. Electrical, thermal and mechanical representations can be combined to examine how package geometry, material choices and operating conditions affect several failure mechanisms at once. Physical testing remains necessary, but modelling can narrow the combinations that need to be built and expose conflicts between design objectives earlier.
Die to die interfaces are already moving from specification work into silicon validation. Racyics has taken a UCIe physical layer into test silicon, demonstrating an x16 interface at 4 and 8 Gbit/s per pin. Automotive deployment has to place comparable links inside a package that can also meet vehicle power, thermal and lifetime requirements.
The e²LEAD demonstrator brings advanced packaging, power electronics, thermal management, virtual engineering and digital twin methods into the same hardware programme. That integration is more demanding than proving each element separately because interfaces between subsystems often determine the final limit on bandwidth, temperature, reliability or maintainability.
The project record covers work from March 2023 to August 2026, although the Xecs project page still lists the administrative status as running. Its technical output is centred on the package as an active part of the compute system, where data paths, power conversion and heat removal have to be engineered together rather than added around a processor after the silicon design is complete.
As vehicle compute platforms absorb more perception, control and automated driving workloads, package design will carry more of the burden of keeping those functions electrically stable and thermally manageable. e²LEAD has focused on that boundary, producing methods and demonstrator hardware for automotive chiplet systems that have to survive conditions far removed from a controlled data centre rack.
