IN Brief:
- The pin-compatible Astra SR210, SR230, and SR250 offer 200, 300, and 400 GOPS of neural acceleration respectively.
- The architecture combines Arm Cortex-M85 and Cortex-M52 cores with up to 8 MB of SRAM and integrated custom DRAM.
- Industrial variants add Gigabit Ethernet with TSN and two CAN FD interfaces; PSA Level 3 and Common Criteria EAL4+ remain stated security targets.
Synaptics has introduced the Astra SR200 family of multimodal edge AI processors, combining Arm Cortex-M85 and Cortex-M52 cores with integrated memory and neural acceleration. The three pin-compatible devices are intended for equipment that must handle sensing, control, vision, or audio locally without the power and software overhead of a larger application processor.
The SR210, SR230, and SR250 provide 200, 300, and 400 giga operations per second (GOPS) of neural processing capability respectively. Synaptics calls the architecture an extended microcontroller, or xMCU, reflecting its combination of conventional embedded control functions with dedicated processing for machine learning and multimedia.
The high-performance Cortex-M85 runs at up to 400 MHz in the SR210, 600 MHz in the SR230, and 800 MHz in the SR250. Their Cortex-M52 efficiency cores operate at 100 MHz, 150 MHz, and 200 MHz respectively. Separating the two processing roles allows time-sensitive monitoring and background work to be assigned differently from more demanding application tasks.
All three devices use a common flip-chip ball grid array package layout and share a development environment. A product family can therefore use different performance grades without requiring a wholly different circuit board connection arrangement, although the actual system design must still accommodate differences in memory capacity, interfaces, and electrical consumption.
The Torq neural engine incorporates Coral NPU technology developed with Google Research. It is intended to accelerate convolutional and transformer-based networks as well as fully connected models. Acceleration reduces the amount of general-purpose processor time needed for supported operations, but the application must still provide suitable model data, memory bandwidth, and software support.
Memory is a significant departure from a conventional microcontroller design. The SR200 architecture combines up to 8 MB of SRAM with integrated custom DRAM that can scale to hundreds of megabytes. Local memory capacity determines whether a processor can hold model parameters, intermediate results, and camera buffers without relying on separate memory devices or transferring data repeatedly through a narrower interface.
Synaptics describes the integrated DRAM as operating at substantially lower power than typical system DRAM for its intended workloads. The claimed reduction depends on the architecture and application rather than representing a measured energy saving for every embedded product. Capacity and memory access patterns must be assessed alongside the headline NPU throughput.
The family also differentiates the amount of multimedia hardware available. SR210 targets always-on voice or sensing with a single camera or display path, while SR230 adds a combination of vision, display, and optional audio processing. SR250 accommodates dual vision and display paths, with dedicated image signal processing and graphics capabilities for more complex devices.
An optional Cadence Tensilica HiFi 5 digital signal processor addresses audio and acoustic processing, while distinct power domains allow some monitoring functions to remain active when more demanding processing resources are inactive. The always-on functions include voice activity detection and wake-up operations, enabling equipment to respond to an event without keeping every processing block continuously powered.
Industrial variants add a Gigabit Ethernet interface with Time-Sensitive Networking support and two CAN FD controllers. These interfaces are relevant when AI processing is combined with networked control, distributed sensors, or robotics, although deterministic behaviour depends on the complete network configuration, software timing, and operating conditions.
Other connections include USB 2.0, high-speed serial flash and storage interfaces, and peripheral buses such as SPI, I2C, and I3C. These interfaces provide options for sensor acquisition and external equipment, but their available configuration and pin allocation have to be checked for the selected processor variant.
Security functions include secure boot, hardware isolation, cryptographic acceleration, device lifecycle controls, and tamper detection. Synaptics identifies PSA Level 3 and Common Criteria EAL4+ as design or certification targets; the release does not establish that the complete family has already obtained both independent certifications.
The software environment includes Zephyr RTOS and the open-source Torq compiler, based on MLIR and IREE technologies. Synaptics is also expanding its Coralboard developer ecosystem, although the separate availability update for those boards is distinct from the new SR200 semiconductor family.
Synaptics has not specified a volume production date or customer deployment total for each part. Selection for an industrial device will depend on sustained model performance, memory capacity, interface availability, thermal constraints, and the engineering effort required to validate the complete application.
