Faraday validates EtherCAT Ethernet PHY for ASICs

Faraday Technology has introduced an enhanced 10/100 Ethernet physical layer IP block supporting EtherCAT communication, with completed interoperability and electromagnetic immunity testing intended to simplify its integration into industrial ASICs.

The design is available for implementation using compatible UMC semiconductor processes. Faraday reports EtherCAT transmission times below 100 microseconds and synchronisation accuracy better than 0.1 microseconds using the protocol’s Distributed Clocks mechanism.

Validation has included testing against the ETG.7000 EtherCAT Conformance Test Specification and relevant parts of the IEC 61000-4 electromagnetic compatibility series. The company has assessed the PHY’s behaviour under several electrical disturbances associated with industrial environments.

The Ethernet physical layer provides the electrical interface between a digital network controller and the transmission medium. It converts digital information into signals suitable for transmission and processes received signals so that the connected controller can recover the data.

In an industrial ASIC, this function can be integrated alongside application processing and control circuitry. Combining these elements within one semiconductor device may reduce the number of separate interface components required on the PCB.

Integration does not remove the need for external supporting hardware. Magnetic components, connectors, transient protection, and suitable PCB routing may still be required, depending on the interface architecture and the equipment in which it is installed.

Industrial Ethernet interfaces operate close to equipment capable of producing substantial electrical interference. Motor drives, switching power supplies, contactors, and solenoid valves can generate voltage changes and transient currents that couple into nearby electronic circuits.

Interference can reach a communication interface through power connections, signal conductors, grounding arrangements, or electromagnetic coupling. If the resulting disturbance exceeds the interface’s tolerance, the equipment may experience corrupted data or interruptions to communication.

Faraday combines digital signal processing with analogue circuit design to improve the physical interface’s resistance to these effects. Its testing programme includes electrostatic discharge, radiated radio-frequency fields, electrical fast transients, surge events, and conducted radio-frequency interference.

The individual assessments address different disturbance mechanisms. Electrostatic discharge can introduce a rapid high-voltage pulse, while an electrical fast transient test applies bursts of short disturbances associated with switching activity.

Surge testing examines a different class of electrical disturbance, generally involving greater energy than a typical electrical fast transient. Radiated and conducted radio-frequency tests assess susceptibility to interference arriving through the surrounding electromagnetic field or connected conductors.

Faraday also carried out an extended electrical fast transient test lasting at least one hour, using solenoid valves to generate repeated high-frequency disturbances. The test was intended to assess communication integrity and the behaviour of the PHY’s protection under sustained switching activity.

The completed testing provides evidence about the IP implementation under the selected conditions. It does not establish that every ASIC or finished industrial machine incorporating the design will automatically comply with all applicable EMC requirements.

Physical layout, power distribution, packaging, and nearby circuitry can change the electrical environment experienced by a PHY after it has been integrated into a larger semiconductor device. Further verification is therefore required during the ASIC implementation process.

EtherCAT provides a communication method for exchanging process data between industrial controllers and connected devices. Its Distributed Clocks mechanism allows participating equipment to maintain closely coordinated timing, supporting applications such as multi-axis motion control.

Synchronised operation is important when several drives contribute to the movement of one machine. A robot or automated handling system may require different axes to respond to coordinated commands without introducing unwanted timing differences between them.

Faraday’s reported synchronisation accuracy relates to the validated communication arrangement. It should not be interpreted as a guarantee of the positioning accuracy or complete control-loop response of every machine using the interface.

Likewise, a transmission time below 100 microseconds describes performance under the company’s specified test conditions. Complete network timing also depends on the controller, connected devices, communication cycle, software, and network configuration.

Testing against ETG.7000 is intended to establish conformity and interoperability of the relevant EtherCAT implementation. Interoperability matters because industrial networks frequently combine controllers, drives, and peripheral equipment from different suppliers.

Providing a prevalidated PHY can reduce uncertainty during ASIC design, particularly where the physical interface must operate reliably while sharing a chip with processing and control circuitry. Customers must nevertheless complete the verification appropriate to their own semiconductor implementation.

Faraday plans to expand its industrial Ethernet IP portfolio with technologies including 10/100/1000BASE-T1 and Single Pair Ethernet. Those interfaces are future development directions, not additional capabilities established by the newly validated 10/100 PHY.

The enhanced PHY gives industrial semiconductor developers a tested starting point for implementing EtherCAT communication. Its eventual use in production equipment will depend on ASIC integration, system-level testing, and qualification against the requirements of the intended application.