IN Brief:
- ChipStack's new RTL Generation Agent can create and revise RTL from high-level design requirements.
- Cadence reports average area reductions of 24% and power reductions of 18% against foundation-model-only generation in early evaluations.
- Honda R&D is evaluating the technology, with selected customer access expected during Q4 2026.
Cadence has expanded its ChipStack AI Super Agent with an RTL Generation Agent that can turn higher-level specifications into register-transfer-level designs and revise existing RTL against new functional, power, performance, and area requirements.
The addition moves ChipStack further towards the front end of semiconductor development. The system already covers autonomous verification and debugging, while the new agent introduces code creation and modification before those checks take place. Engineers can provide design requirements in natural language, after which the agent generates RTL and invokes Cadence tools to evaluate the result.
Cadence says early evaluations produced an average 24% reduction in area and an 18% reduction in power compared with RTL generated using a foundation model alone, while maintaining functional accuracy in the designs tested. Those figures are vendor results rather than an industry-wide benchmark, but they illustrate why the company is coupling generative AI to existing EDA engines instead of treating code generation as the end of the task.
Hardware description differs from conventional software because design choices eventually become physical structures. RTL determines logic, state, data movement, memory organisation, switching activity, and timing relationships that later influence synthesis, floorplanning, routing, and power consumption. Code can be syntactically correct and functionally plausible while still producing an inefficient or difficult physical implementation.
ChipStack addresses that problem by placing specialist agents inside a wider orchestration layer. Cadence describes a hierarchy in which the super agent coordinates task-specific agents, while established design and verification engines provide deterministic analysis. The AI therefore has access to measured engineering results rather than relying entirely on its own interpretation of the RTL it created.
The RTL Generation Agent can also modify existing designs as requirements change. That is potentially useful for derivative SoCs and established IP, where engineers may need to add functionality, change interfaces, or improve power and area without disturbing verified behaviour elsewhere. Automating the edit is straightforward compared with proving that the resulting design still satisfies its original constraints.
Honda R&D is evaluating the system for automotive SoC development, an application where those constraints are particularly visible. Vehicle processors have to combine performance and power targets with long qualification cycles, functional safety requirements, traceability, and software lifetimes that extend well beyond the development cadence of most AI tools.
ChipStack already applies autonomous AI to verification and debugging, so RTL generation connects design creation more directly with the tools used to test it. The engineering value will depend on whether information survives that loop. A generated block that passes an isolated functional check can still create timing, power, testability, or integration problems when it is placed inside a larger SoC.
Cadence is attempting to preserve that context through what it calls a shared mental model covering design intent, hierarchy, specifications, and relationships between tasks. The objective is to prevent each agent from operating on an isolated prompt when later decisions depend on assumptions made during architecture or RTL creation.
This does not remove conventional sign-off. Static timing analysis, formal verification, simulation, power analysis, physical verification, and implementation checks still determine whether the design can progress. An autonomous workflow can shorten repetitive iterations, but it can also propagate a poorly defined requirement quickly if the specification entering the system is incomplete or inconsistent.
PPA optimisation is therefore a more demanding measure than raw code generation speed. Saving time when creating RTL has little value if synthesis produces excessive logic, timing closure becomes harder, or downstream verification effort increases. Connecting the generation agent to analysis tools gives Cadence a mechanism for testing those consequences before the design reaches the later stages of implementation.
The expanded ChipStack capability is expected to reach selected early-access customers in the fourth quarter of 2026. Production programmes will provide a harder assessment than the initial evaluations, particularly where generated RTL has to survive integration, verification, physical design, and sign-off without moving the saved engineering effort further down the flow.
