IN Brief:
- Diodes Incorporated has launched a six-output PCIe 7.0 clock generator for AI infrastructure platforms.
- The PI6CG33A06 delivers 25MHz and 100MHz reference clocks with less than 30fs RMS jitter.
- Integrated termination reduces external resistor count, PCB layout complexity, and timing-related power consumption.
Diodes Incorporated has introduced the PI6CG33A06, a six-output ultra-low jitter clock generator designed for PCI Express 7.0 systems while maintaining compliance with earlier PCIe generations.
The device was announced at the PCI-SIG Developers Conference and targets servers, networking equipment, high-performance computing systems, and data centre platforms used in next-generation AI infrastructure. It generates 25MHz and 100MHz reference clocks and achieves RMS jitter of less than 30fs.
That figure is below the 67fs maximum requirement for PCIe 7.0 and below the 80fs level defined by Intel’s CK440Q specification. The additional margin helps engineers manage signal-integrity challenges across complex PCB traces, connectors, packages, and high-speed system layouts.
The PI6CG33A06 provides a stable reference clock for 128GT/s PCIe links, supporting the bandwidth demands of 800G and 1.6T networking and advanced AI accelerators. Accurate timing at these data rates is critical to maintaining link stability, especially where long traces, dense boards, connectors, and multiple high-speed interfaces all contribute to jitter budgets.
The clock generator uses Diodes’ low-power, high-speed current-steering logic technology with integrated termination. The design reduces clock-related power consumption by at least 50% compared with traditional HCSL solutions and lowers thermal load in high-density AI server racks.
Integrated termination also removes the need for up to 24 external resistors, reducing bill-of-materials cost, simplifying PCB layout, and freeing board space. Each of the six outputs includes an individual output-enable pin, giving designers more control over power management and system operation.
The device supports Intel CK440Q-Lite specifications and is intended for use in existing server clock architectures, allowing designers to reuse established system approaches while improving timing performance. The PI6CG33A06 is supplied in a 40-pin, 5mm by 5mm VQFN package and is priced from $2.80 in 3,000-piece quantities.
Clock generators are often less visible than processors, accelerators, or memory devices, but they become critical as serial-link speeds rise and timing margins shrink. At PCIe 7.0 rates, reference clock quality has a direct effect on compliance, eye margins, bit error performance, and long-term link stability.
AI infrastructure places additional strain on timing distribution. Servers and accelerator platforms now combine dense processor complexes, high-speed networking, PCIe fabrics, retimers, storage, and memory expansion in compact thermal envelopes. Timing circuitry has to support higher bandwidth without adding avoidable power, heat, or routing complexity.
Sub-30fs jitter gives designers additional headroom across the signal path. Connectors, backplanes, PCB materials, routing density, and package transitions all contribute to loss and distortion. A stable reference clock reduces one source of uncertainty in the system budget and gives engineers more margin elsewhere in the design.
The integration of termination is also useful in dense layouts. Removing external resistors reduces component count, simplifies routing around high-speed devices, and supports cleaner board implementation. For PCIe 7.0 platforms moving towards production, timing components such as the PI6CG33A06 form part of the practical work needed to turn interface specifications into deployable server and accelerator systems.
