IN Brief:
- Keysight’s new PCIe 7.0 RX test application targets receiver validation at 128GT/s.
- The solution combines N5991PB7A software with M8050A BERT hardware, M8042A pattern generation, and M8043A error analysis.
- Receiver stress calibration is becoming a key bottleneck for next-generation ASIC interoperability.
Keysight Technologies has expanded its PCIe 7.0 physical-layer test portfolio with a new receiver test application for validating receiver performance at 128GT/s.
The PCIe 7.0 Receiver Test application extends Keysight’s existing PCIe 7.0 transmitter test capability, giving engineers broader transmitter-to-receiver coverage for next-generation compute, AI, and data-cententre designs. The receiver application is built around stress signal calibration and receiver characterisation for ASIC validation.
The hardware setup combines Keysight’s M8050A BERT family with the M8042A 120GBaud pattern generator and M8043A error analyser. The software element is the N5991PB7A Receiver Test Automation Software, which supports calibration and control of PCIe 7.0 receiver stress signals.
The N5991PB7A software is designed to maximise instrument throughput, guide receiver stress signal calibration, assist with impairment setup for the M8050A pattern generator, and generate calibration reports for further analysis. The product page notes guided setup with automated TP3 and TP2 receiver stress signal calibration procedures, plus exportable reports for post-processing.
The receiver test solution supports ASIC development in common clock mode. It is intended to reduce manual setup effort, improve repeatability, and expose receiver weaknesses earlier in the validation process. Keysight will show the PCIe 7.0 receiver test at the PCI-SIG Developers Conference in Santa Clara.
PCIe 7.0 doubles the data rate from PCIe 6.0, moving to 128GT/s. That reduces available signal margin across receiver tolerance, channel loss, jitter, calibration error, and measurement repeatability. Physical-layer validation therefore becomes more demanding well before a device reaches final compliance testing.
Receiver testing is one of the more difficult parts of high-speed interface validation because the receiver must be challenged with a known stressed signal that remains aligned with specification conditions. An incorrectly calibrated stress signal can produce misleading results, either by failing a device unfairly or by masking margin problems that appear later during interoperability testing.
AI and data-centre ASIC development is increasing demand for faster serial I/O. Accelerators, CPUs, switches, storage controllers, and high-speed interconnect devices all depend on reliable links between processors, memory systems, backplanes, and peripheral devices. As speeds increase, validation data has to guide design decisions earlier, not simply confirm compliance at the end of development.
Automation is becoming essential at these speeds. Manual receiver test setup is slow, specialist, and vulnerable to variation between engineers and labs. Automated calibration does not remove the need for signal-integrity expertise, but it can make setup more repeatable, reduce operator variation, and shorten the route to usable validation data.
Keysight’s latest PCIe 7.0 receiver test application addresses a growing pressure point in test and measurement. Standards cycles are compressing, AI infrastructure is driving faster interfaces into production roadmaps, and validation teams need physical-layer tools that keep pace with receiver complexity. For ASIC developers, 128GT/s receiver characterisation is becoming central to interoperability, schedule control, and design confidence.
