IN Brief:
- Faraday has made a silicon-proven MIPI C-PHY v2.0 and D-PHY v2.5 combo PHY available on UMC 14nm FinFET.
- The design supports up to 3.0Gsps per C-PHY trio or 4.5Gbps per D-PHY lane, with an area reduction exceeding 30% claimed for shared circuitry.
- Built-in self-test, D-PHY receive de-skew and Alternate Low Power mode are included for integration into imaging SoCs.
Faraday Technology has made a dual-protocol MIPI physical interface available for customer system-on-chip designs using UMC’s 14nm FinFET manufacturing process. The silicon-proven C/D Combo PHY supports C-PHY v2.0 at up to 3.0 giga-symbols per second per trio and D-PHY v2.5 at up to 4.5Gbps per lane. Faraday says sharing circuit blocks between the two interfaces reduces the IP area by more than 30% compared with its separate implementation approach.
Imaging SoCs must move sensor data into processing hardware without devoting excessive silicon area to separate analogue interfaces for every operating requirement. C-PHY and D-PHY use different physical signalling arrangements, so merely adding support for both protocols in an SoC would normally impose additional interface circuitry and connection requirements. A configurable PHY allows the design team to reuse specified circuitry rather than duplicate a complete interface.
MIPI D-PHY transfers data over differential signal lanes and is widely used between image sensors, displays and their controllers. C-PHY uses three-wire groups known as trios, encoding information through transitions among the wires. A rate expressed as symbols per trio is not directly interchangeable with a D-PHY figure quoted in bits per second per lane, because the signalling and encoding differ. Faraday’s two published maxima must therefore be compared using the relevant protocol architecture and configured channel count.
The company identifies shared pins, digital logic, input and output buffers, phase-locked loops and calibration circuits as the principal means of reducing area. The phase-locked loop provides timing signals needed by the physical interface, while calibration functions compensate for relevant circuit and signalling variations. Reusing these blocks has potential benefits in silicon footprint and layout complexity, although the 30% area reduction is a company comparison whose exact reference configuration is not specified in the announcement.
The combo PHY offers scalable configurations to match different data throughput requirements, enabling a design to use the protocol appropriate to its sensing and power objectives. Faraday suggests C-PHY for demanding video transfers and D-PHY for lower-power or standby operation. Actual power savings will depend on the selected operating mode, lane configuration, clock behaviour and traffic pattern; no measured watts-per-gigabit comparison has been published for the announced IP.
At the receiver, high-speed de-skew calibration is incorporated for D-PHY operation. Skew arises when signals that should reach a receiver together arrive at different times because of transmission paths and circuit variations. As signalling rates rise, the acceptable timing window narrows and skew can become a source of errors. A receiver able to compensate for timing mismatch may therefore offer useful margin, but the final board and package routing still require suitable signal integrity design.
Built-in self-test is available for both protocols, allowing the interface to be exercised as part of manufacturing test rather than relying solely on system-level functional checks. Faraday also includes an Alternate Low Power mode, providing another operating choice when continuous high-speed communication is unnecessary. These functions could reduce some validation effort, but test coverage, diagnostic capability and production cost will depend on how the PHY is integrated into the completed chip and test programme.
Implementing an analogue PHY on UMC’s 14nm FinFET process requires characterisation against the electrical and process constraints of that semiconductor node. Silicon proven means Faraday has validated an implementation in fabricated silicon; it does not by itself establish performance across every permitted SoC floorplan or package. Integrators must still work through power delivery, analogue placement, ESD protection, package connections and the interface timing budget for their own design.
Faraday positions the new block for vision AI, automotive smart sensing, machine vision and imaging devices. In these systems, camera interfaces may need to operate at different resolutions or frame rates while processors manage tight thermal and power budgets. The choice between a shared combo PHY and separate interfaces remains an architectural decision involving supported sensors, required bandwidth, die area and verification effort.
Faraday is offering the 14nm IP alongside ASIC development and Arm-based integration services, enabling customers to incorporate the interface within a broader chip design programme. The company has not disclosed customer tape-outs, device shipment quantities or independent measurements supporting its area and power claims. The specifications establish the interface capabilities available to SoC teams, while the resulting benefits remain dependent on the host chip and system design.
