IN Brief:
- NbTiN Josephson junction density reaches 3.8 million devices per square centimetre on a 300mm CMOS-compatible process.
- Three routing layers include NbTiN wires scaled to 30nm, around one-tenth the width achievable with conventional niobium technology.
- The programme combines process development, design enablement, and heterogeneous integration for future computing and control applications.
imec has demonstrated a three-metal-level superconducting circuit platform built with niobium-titanium-nitride, pushing Josephson junction density to 3.8 million devices per square centimetre while scaling superconducting wiring to 30nm. The work is being presented at the 2026 Applied Superconductivity Conference and uses 300mm CMOS-compatible processing, placing conventional semiconductor manufacturing methods at the centre of a technology that has historically sat well outside mainstream logic fabrication.
The circuits use NbTiN/α-Si/NbTiN Josephson junctions with diameters down to 150nm. Imec has also demonstrated three layers of NbTiN routing, including wires and vias intended to support inductors, passive transmission lines, ground planes, and clock or power resonators. The 30nm wire width is roughly one-tenth of the scale achievable with conventional niobium-based superconducting technology, according to the research organisation, while both junction critical-current density and interconnect critical current can be tuned for different target applications.
Dense superconducting logic requires more than smaller switching elements. It also needs wiring, power distribution, clocking, and interfaces that preserve the low-loss characteristics of the devices as circuit complexity rises. Conventional niobium processes have delivered working superconducting logic for years, but their feature sizes and integration density remain well behind advanced CMOS, leaving a substantial gap between laboratory devices and the scale required for processors with useful system-level complexity.
Imec is approaching that gap as a process-and-integration problem rather than a single-device exercise. Its programme combines superconducting process development with design enablement and 2.5D or 3D heterogeneous integration, allowing superconducting logic to be considered alongside other compute and interface technologies. That route also reflects the likelihood that memory, analogue functions, photonics, or conventional control electronics will continue to operate alongside low-temperature logic rather than being rebuilt in one superconducting process.
Potential applications include high-performance computing and AI accelerators, where energy consumed in moving data can be as important as switching energy in the logic itself. Superconducting interconnects offer effectively zero DC electrical resistance below their critical temperature, reducing resistive losses across local wiring. Josephson junction logic also switches with very small energy per operation, although complete systems still have to account for cryogenic cooling, packaging, interfaces, and the energy cost of moving data between temperature domains.
The 300mm process compatibility is significant beyond wafer diameter alone. Mature semiconductor development depends on repeatable process control, design rules, metrology, yield learning, and a route from isolated devices towards multi-level integrated structures. Bringing superconducting devices into a manufacturing environment that already supports those disciplines gives foundries and system companies a more recognisable basis for evaluating the technology, even if commercial-scale superconducting processors remain a longer-term proposition.
Process tunability adds another useful degree of freedom. Imec reports that the critical-current density of the Josephson junctions and the critical current of the interconnects can be adjusted, allowing the same material system to be explored across different circuit requirements. Logic, resonant structures, transmission lines, and interfaces do not necessarily favour identical electrical parameters, so a practical process has to provide controlled options without turning every circuit into a bespoke fabrication flow.
Scaling the routing is particularly relevant because interconnect density can become a practical limit before the active devices themselves. Narrower superconducting wires allow more signals to pass through a given area, but they also tighten requirements for dimensional control, via resistance, defect density, and current handling. Those process variables have to remain stable across a full 300mm wafer if circuit density is to translate into manufacturable die rather than isolated demonstrations.
The next engineering test is scale. Larger circuits will have to preserve junction uniformity and routing performance while adding realistic clock distribution, power delivery, interfaces, and thermal constraints. Imec’s latest structures establish that NbTiN can be patterned at substantially smaller dimensions than conventional niobium technologies on a CMOS-compatible 300mm platform; repeatable yield and system integration will determine how far that density can be translated into useful compute hardware.
