IN Brief:
- Intel says High-NA EUV is already used on selected production layers for a subset of Panther Lake processors.
- More than one million wafers have been processed across tool certification, R&D, and volume-manufacturing activity.
- Intel and ASML are supporting current 6-inch-mask approaches while developing a future 6×12-inch mask ecosystem.
Intel Foundry and ASML say High-NA EUV is now being used on selected volume-production layers at Intel, with more than one million wafers processed across tool certification, research and development, and manufacturing activity. The companies are also working on larger photomasks intended to make 0.55-NA lithography easier to deploy across a wider range of advanced chip designs.
The one-million-wafer figure combines several stages of development rather than representing one million commercial High-NA production wafers. Intel says the total includes early tool certification and testing, R&D work, and volume manufacturing on selected layers for a subset of Intel Core Ultra Series 3 processors, code-named Panther Lake.
Intel reports that overlay, throughput, and equipment availability are meeting its expectations for that work. It also says Intel 18A products using High-NA on selected layers are delivering performance that meets or exceeds comparable layers patterned on the established 0.33-NA NXE EUV platform.
Those statements move the discussion beyond resolution test structures because High-NA has to operate inside a complete manufacturing flow. Lithography performance must coexist with deposition, etch, metrology, overlay control, defect management, and yield before a higher numerical aperture becomes useful in production.
The 0.55-NA optical system provides higher resolution than current EUV tools but exposes a smaller field with today’s standard mask format. Intel says customers can work within that constraint by floorplanning designs inside the available field or using stitching supported through its process-design-kit environment.
Stitching allows separate exposures to form a larger pattern, but it transfers part of the manufacturing problem into design rules, overlay control, and verification. Customers therefore need the relevant restrictions represented in EDA tools and PDKs before a design reaches tape-out rather than discovering them when masks are already being prepared.
Intel and ASML are simultaneously backing development of a 6×12-inch mask format. A larger mask could reduce the need for stitching on some future designs, but the change extends beyond the mask itself because writers, inspection systems, handling equipment, fab automation, materials, and standards all have to support the format.
Intel says it has spent more than three years working with mask makers, automation suppliers, EDA companies, materials providers, and semiconductor manufacturers on that ecosystem. The existing 6-inch route will continue to be used in parallel, giving customers an immediate path while the larger-format infrastructure develops.
The release, dated 7 September, also clarifies the maturity of Intel’s High-NA programme. Intel installed the first commercial EXE system in 2024, while the latest disclosure focuses on production layers, wafer counts, overlay, throughput, availability, stitching, and customer design enablement rather than first-light or resolution records.
Selective insertion remains central to the economics. A High-NA exposure may replace more complicated multi-patterning on a difficult layer, but established 0.33-NA EUV can remain preferable elsewhere once equipment cost, process maturity, throughput, mask requirements, and yield are included.
Intel’s current manufacturing use therefore does not imply that High-NA has replaced conventional EUV across Panther Lake or Intel 18A. It shows that selected 0.55-NA layers have progressed into a volume-production environment while the company develops the design and mask infrastructure needed to broaden its use.
