IN Brief:
- Puma 9 combines DOCSIS 3.1, 3.1+, and 4.0 support on one 8nm SoC with field upgrade capability.
- Five OFDM channels provide up to 12Gbit/s downstream operation in a DOCSIS 3.1+ configuration, according to MaxLinear.
- The platform adds DDR5 support, a MaxAI NPU, Wi-Fi 8 integration, and post-quantum cryptography readiness for longer-lived gateway designs.
MaxLinear has introduced Puma 9, an 8nm DOCSIS gateway system-on-chip designed to support DOCSIS 3.1, 3.1+, and 4.0 on one hardware platform. The device adds DDR5 memory compatibility, provision for Wi-Fi 8 gateways, a MaxAI neural processing unit, and post-quantum cryptography readiness for customer premises equipment expected to remain deployed through several network upgrade cycles.
The platform can be configured through field upgrades as an operator moves between DOCSIS generations. MaxLinear says this allows equipment to be installed against a DOCSIS 3.1 network and later enable 3.1+ or 4.0 functions without replacing the gateway hardware. Five OFDM downstream channels support up to 12Gbit/s in the company’s DOCSIS 3.1+ configuration.
The five-channel configuration is also a reminder that DOCSIS capability is determined by the complete RF and network environment, not the SoC alone. MaxLinear’s 12Gbit/s figure is a platform capability for the stated 3.1+ configuration; service speeds available to a subscriber will depend on spectrum allocation, plant condition, operator provisioning, shared capacity, and the rest of the gateway design.
Separating gateway replacement from network upgrades addresses a persistent problem in cable access. Customer premises equipment and outside-plant infrastructure rarely reach the end of their useful lives at the same time, yet a hardware choice can tie the two investment cycles together. A common silicon platform gives operators and gateway manufacturers more scope to qualify one design while enabling additional capability as the network behind it changes.
Puma 9 also supports DDR5. Broadband gateways can remain in production and service for years, so memory availability becomes a lifecycle consideration rather than a simple performance choice. As suppliers move capacity towards newer DRAM generations, dependence on an older memory type can expose a long-lived equipment programme to rising cost or reduced component availability.
The integrated MaxAI NPU provides acceleration for local workloads including quality-of-service optimisation and network management functions. Dedicated processing can keep bounded inference tasks away from the main application processors, although the useful workload in a deployed gateway will still depend on software, memory bandwidth, thermal limits, power consumption, and the operator’s service model.
Security functions are being designed for the same long lifecycle. MaxLinear lists post-quantum cryptography readiness and support for requirements associated with NIST IR 8425A, the EU Radio Equipment Directive, and the Cyber Resilience Act. A broadband gateway combines persistent network access, remote management, and a large installed base, so update support and cryptographic agility can remain relevant long after the silicon has left production.
MaxLinear is making Puma 9 available to broadband operators and OEM partners developing DOCSIS gateways and eMTA products. Askey and Gemtek are developing systems around the platform, while FRITZ! and Mediacom are among the organisations evaluating it. Those engagements move the device beyond a specification sheet launch, but gateway deployment still depends on RF design, board layout, memory qualification, Wi-Fi integration, thermals, certification, operator software, and interoperability.
The company estimates that Puma 9 can reduce customer premises equipment costs by 30% to 50% compared with alternative DOCSIS 4.0 approaches. That is a supplier projection rather than an independently established saving, and the result will depend on the final bill of materials, Wi-Fi implementation, production volume, qualification requirements, and operator configuration.
Integration can nevertheless reduce the number of hardware variants an OEM has to maintain. A single SoC covering DOCSIS 3.1 through 4.0 can limit duplicated board designs and software branches while giving operators more flexibility over when particular services are enabled. The commercial value will depend less on the headline percentage than on how much requalification and field replacement the common platform actually avoids.
Puma 9 is available now to operators and OEM partners rather than as a future silicon announcement. The next evidence will come from completed gateway designs and operator qualification, where the combined DOCSIS, Wi-Fi, memory, AI, and security functions have to work within the cost, power, thermal, and reliability limits of mass-produced CPE. Access-network silicon tends to spend far longer in the field than it does in a launch presentation, which makes that lifecycle engineering the more durable part of the specification.
