Microchip reaches PIC64-HPSC space processor testing milestones

Microchip has reached further development milestones for its PIC64-HPSC spaceflight computing series, with early radiation characterisation of the PIC64-HPSC1000-RH processor demonstrating operation through a total ionising dose of 200krad(Si). The company also reports successful single-event latch-up testing to a linear energy transfer of 78.2MeV·cm²/mg under stated test conditions. Completed system-controller single-event-effects characterisation found no uncorrected errors or external resets in the tests performed. These are reported experimental results, not evidence that the complete processor family has finished all possible flight qualification.

The distinction between tested performance and product rating is important. Microchip describes the radiation-hardened device with a 100krad(Si) total-dose rating, even though early radiation characterisation reached 200krad(Si) in specified conditions. A higher result in a particular test does not automatically change a guaranteed qualification limit. Mission designers should compare the published rating and underlying radiation-test report with their own dose estimates, shielding assumptions and required operating margins rather than selecting the processor on the highest reported test result.

The HPSC architecture is built around 64-bit multicore RISC-V processing, aimed at the growing demand for onboard computation in satellites and other spacecraft. Space systems increasingly need to process image, sensor and control data without sending every operation to ground. That creates pressure for greater computing capability within severe power, thermal and reliability constraints. A suitable device must deliver processing performance while maintaining deterministic behaviour for critical functions and recovering from errors in a harsh radiation environment.

Single-event effects differ from accumulated total-dose degradation. A charged particle passing through semiconductor material can disturb a logic state, cause a transient error or, in an unfavourable design, trigger a sustained parasitic current path. The reported latch-up test result concerns one class of that risk under a tested particle energy and operating configuration. Absence of a particular failure during completed controller tests does not imply immunity to every transient or fault across all processor subsystems, temperatures, voltages and lifetime conditions.

Microchip says early-access customers are evaluating silicon and development kits and beginning software application work. Board partners are developing VPX and VNX+ computing platforms around the device, creating integration options for different spacecraft architectures. These form factors may ease the work of combining processing hardware with compatible chassis and interconnects, but each implementation still needs power, cooling, mechanical and radiation analysis. A development board can help establish software compatibility; it is not the same as a qualified flight computer.

RISC-V gives software teams an established open instruction-set foundation, although a multicore space processor still requires device-specific boot flows, toolchains, drivers and mechanisms for fault supervision. Workloads have to be tested under realistic memory and I/O demands, and developers should identify which tasks can tolerate interruption or recovery. Fault containment between cores and peripheral blocks can matter when software consolidates several spacecraft functions onto fewer processing boards. Thermal modelling also remains necessary because spacecraft generally cannot rely on terrestrial-style convective cooling.

System-level resilience will also involve memory protection and error-handling policies. A processor may detect and correct certain faults internally, but spacecraft software needs clear reporting and recovery paths for disturbances that escape local correction. Watchdogs, redundancy strategies and state preservation can help manage faults, subject to the architecture and mission criticality. The reported absence of uncorrected errors in completed controller tests is encouraging evidence for that portion of the design, but it cannot replace verification of the full hardware and software stack under representative workloads and radiation exposure.

The current milestone is therefore a progression in silicon characterisation and customer integration, not a completed deployment. Evaluation and development kits are available to selected programme participants while board suppliers work on supported platforms. The next evidence engineers will need includes full device-level qualification data, software maturity and system testing under their specific mission conditions. Those results will determine how far PIC64-HPSC moves from promising spaceflight silicon towards dependable onboard computing platforms.