Rapidus and HCLTech open semiconductor engineering centres

Rapidus and HCLTech have opened two semiconductor engineering centres in India to support the Japanese chipmaker’s advanced logic development. The facilities are located in Bengaluru and Hubli, and their work spans mask design, design infrastructure, process design kits, layout and design-technology co-optimisation. The centres add engineering capacity and tools that can support future foundry customers; they are separate from the construction and qualification of Rapidus’s Japanese wafer fabrication operations. The companies also plan to build an Indian talent pipeline supporting Rapidus’s longer-term semiconductor engineering requirements in Japan.

A process design kit, or PDK, provides the information required to turn a circuit design into a layout that can be manufactured on a given semiconductor process. It contains design rules and models describing device and interconnect behaviour, with supporting verification data. When a process is still developing, changes to transistor characteristics or fabrication constraints can affect designers’ assumptions. Creating and maintaining reliable design kits is therefore central to establishing a usable foundry service, even before high-volume wafer output begins.

Mask and layout development introduces another layer of complexity. Advanced nodes rely on intricate patterning and tightly controlled geometries, so engineers must verify that a design respects both physical rules and electrical performance requirements. Design-technology co-optimisation attempts to resolve conflicts between circuit architecture and manufacturing capability early, rather than leaving the fabrication team to discover them after tape-out. This work can shorten iterations when its models faithfully represent the actual process, but inaccurate assumptions create risks across an entire design programme.

Rapidus’s wider ambition is to build leading-edge manufacturing capability in Japan, supported by an international design ecosystem. India has a substantial engineering workforce and established semiconductor design-service activities, making dedicated centres a way to add capacity in specialist tasks. The work needs close coordination across time zones and organisations because process models, design documentation and customer intellectual property are sensitive. Secure data access and configuration control will matter as much as the number of engineers recruited.

The development can help Rapidus support prospective customers who need more than wafer-processing capacity. Foundry users require libraries, verification flows, layout guidance, testing interfaces and dependable channels for resolving design-rule problems. Bringing these elements together takes time, particularly when they must be revised as manufacturing process data improves. An inaugurated engineering office should not be mistaken for a completed PDK covering every device type or a commercial commitment by specific chip designers.

There are also practical workforce considerations. Engineers with deep knowledge of physical implementation, timing closure and yield-sensitive layout are scarce, and a project cannot scale simply by adding headcount. Teams need consistent workflows for versioning design rules and managing customer changes, plus a clear understanding of which design artefacts have been validated with silicon. Training and expertise transfer between India and Japan will determine whether the collaboration produces usable engineering capacity.

Process maturity must also be communicated in a form that circuit designers can use. A PDK may include preliminary device models suitable for architectural evaluation before it has the evidence needed for final sign-off. Teams should label those stages and document changes that might alter the behaviour of previously designed circuits. Model correlation against measured silicon is a critical milestone.

Without it, apparent progress in simulation can conceal problems that emerge only after expensive wafers are fabricated. Clear release procedures and technical support channels will therefore shape the value of the new centres. Design engineers also need rapid notification of revised models, because a model update can affect circuit timing or power assumptions in layouts already approaching tape-out.

The centres add an identifiable implementation step to Rapidus’s efforts to assemble a design-to-manufacturing ecosystem. Success will be judged through validated tools, efficient handling of customer designs and eventual silicon results rather than the ceremonial opening. For chip designers assessing future access to Rapidus processes, the immediate questions concern PDK maturity, available IP, verification methods and the timetable for accepting real production designs.