MIPS launches three physical AI platforms

MIPS has launched three developer platforms that separate edge AI inference, real-time event processing, and mission-critical embedded workloads rather than treating physical AI as one undifferentiated processor problem. Acies, Actus, and Aegis are described respectively as inference-native, event-native, and safety-native platforms for industrial machines, transport systems, and embedded equipment operating in the physical world.

Acies is the inference-focused member of the trio. MIPS says the platform combines an open, standards-based neural processing unit with an open software stack and a developer-oriented form factor for modern edge workloads. The current announcement does not specify NPU throughput, memory bandwidth, power consumption, numerical formats, or a detailed processor configuration, leaving the initial proposition centred on architecture and development access rather than benchmark leadership.

Actus addresses a different requirement: events that have to be processed within predictable time constraints. MIPS lists motion control, sensor fusion, and predictive maintenance among its target applications. Such systems may use AI algorithms, but their engineering requirements differ substantially from those of a pure inference accelerator because latency and deterministic response can matter more than maximum aggregate operations per second.

Aegis moves further towards mission-critical systems. MIPS describes it as a developer platform for physical AI requiring low-latency and agentic processing with a safety-oriented architecture. The launch does not state a particular ASIL or SIL certification for Aegis itself, nor does it specify the processor implementation underpinning the platform. It should therefore be treated as a development architecture aimed at safety-critical applications rather than as a certified production system.

The three-way division reflects the actual workload inside an autonomous machine. A robot or industrial control system does more than execute a neural network. Sensors generate data, processing identifies what is happening, real-time software has to respond within defined time windows, actuators must be controlled safely, and communications link the machine to neighbouring controllers or higher-level systems. The fastest compute engine is only one element in that closed loop.

MIPS has increasingly organised its portfolio around that distinction through its broader Atlas work, describing physical AI as a cycle of sensing, thinking, acting, and communicating. That framing gives the three new platforms a clearer purpose: Acies concentrates on interpreting information, Actus on reacting to events, and Aegis on systems where the response also has to satisfy more demanding reliability and safety requirements.

The company’s earlier work provides context without establishing that any particular existing processor sits inside the new platforms. MIPS and Green Hills Software have already developed a Safety SDK around the M8500 RISC-V architecture, targeting ASIL-D and SIL 3/4 development flows for motor control, traction inverters, battery management, and other real-time systems. That programme shows the type of safety and toolchain work MIPS is pursuing, but the new Aegis announcement does not identify it as an M8500 product.

The business has also changed materially since becoming part of GlobalFoundries. GF completed its acquisition of MIPS in August 2025 and added Synopsys’ ARC Processor IP Solutions business in June 2026. The combined MIPS and ARC operation now spans RISC-V processor IP, software tools, application-specific processor technology, custom design, and access to GlobalFoundries manufacturing.

GlobalFoundries says the combined portfolio is backed by more than 150 patents and serves more than 300 processor-IP customers. The ARC acquisition also brought ASIP Designer and ASIP Programmer into the organisation, extending the ability to develop application-specific processor architectures rather than relying on fixed off-the-shelf cores for every workload.

MIPS has reinforced its position inside the RISC-V ecosystem as part of the same strategy. In August it became a Premier Member of RISC-V International, with chief technology officer Yankin Tanurhan appointed vice-chairman of the organisation’s board. Open instruction-set standards can make processor customisation and software portability easier, but a commercially useful embedded platform still depends on toolchains, operating systems, middleware, accelerators, interfaces, safety evidence, and production silicon.

That makes the lack of detailed platform specifications the most important limitation of the current launch. MIPS has not published processor configurations, memory hierarchies, accelerator throughput, interfaces, board specifications, pricing, or production schedules for Acies, Actus, and Aegis. Those omissions prevent a meaningful performance comparison with established embedded-AI development systems.

They also create a straightforward set of next milestones. Acies will need measured inference efficiency and supported models, Actus will need credible deterministic timing and control-loop data, and Aegis will need a defined safety architecture and certification pathway. Dividing physical AI according to workload is technically more useful than placing every edge processor under the same AI label, but development platforms earn their place on an engineer’s bench through interfaces, documentation, benchmarks, and a credible route into production hardware.