IN Brief:
- GPT-Synopsys will combine OpenAI models with Synopsys EDA tools and semiconductor engineering knowledge.
- The system is intended to run tools, interpret results, modify designs, and iterate against engineering objectives.
- OpenAI will license Synopsys EDA technology as part of the multi-year development and commercial agreement.
Synopsys and OpenAI are developing a specialist AI model for semiconductor engineering that will work directly with electronic design automation tools, extending their collaboration beyond general-purpose assistants towards systems able to participate in iterative chip design and verification workflows. The multi-year programme will create GPT-Synopsys, with OpenAI licensing Synopsys EDA technology while the two companies work jointly on research, commercialisation, and customer deployment.
Synopsys intends the model to operate design tools, interpret their output, modify a design, and continue iterating towards objectives defined by engineers, including power, performance, and area optimisation, timing closure, and verification closure. Those tasks absorb substantial engineering time because progress is rarely linear: reducing power can affect timing, a physical change can disturb routing or signal integrity, and an apparently successful optimisation can create a new verification problem elsewhere in the design.
A model working effectively in that environment has to retain much more context than a conventional coding assistant, since the significance of one EDA result depends on the constraints, tool settings, preceding runs, and design decisions that produced it. Generating a plausible command or script is relatively easy compared with deciding whether the resulting change has improved the chip, merely shifted a problem, or invalidated assumptions used earlier in the flow.
Synopsys president and CEO Sassine Ghazi has framed the collaboration around shortening chip development without compromising power, performance, area, or first-time-right silicon, which puts the emphasis on engineering closure rather than text generation. GPT-Synopsys will run on OpenAI-hosted infrastructure and is intended to work both with customers’ own agent frameworks and with Synopsys’ existing AI engineering systems.
That places the new model alongside Synopsys’ AgentEngineer and Autopilot platforms, announced in September, although the functions are different. Autopilot provides orchestration, persistent memory, governance, reusable skills, and connections between engineering agents and tools, while GPT-Synopsys is intended to provide deeper semiconductor-specific reasoning within those workflows, reducing the amount of semiconductor knowledge that has to be recreated through prompts and external logic.
Semiconductor design is an unusually unforgiving environment in which to test that proposition because persuasive output is worthless if it fails deterministic checks. Changes to RTL, timing constraints, floorplans, or physical implementation still have to survive functional verification, timing analysis, design-rule checking, power analysis, and sign-off, meaning an AI system can widen the search space or accelerate iteration without weakening the criteria by which the finished design is accepted.
Engineer review therefore remains part of the proposed operating model, and Synopsys is not presenting GPT-Synopsys as an autonomous replacement for sign-off. The more realistic opportunity lies in delegating repetitive exploratory work, running larger numbers of optimisation loops, and presenting engineers with fewer but better-developed options once the tools have already rejected obviously inferior alternatives.
Handling unreleased semiconductor IP creates another constraint, particularly where a hosted model can encounter proprietary architectures, verification results, process-specific data, or customer information long before a device is public. Synopsys says customer-specific design data will not be used to train the model, while deployments will include encryption, configurable data retention, permissions, auditability, and governance controls intended to make model access compatible with existing engineering security policies.
OpenAI’s decision to license the underlying Synopsys tools is equally significant because competence with EDA software cannot be developed entirely from written descriptions of how those tools are supposed to behave. Timing reports, failed constraints, physical-design warnings, verification output, and convergence behaviour all contain structured information that has to be interpreted in the context of the tool producing it, giving the development programme access to the working environment in which the model’s engineering ability will actually be judged.
Early customer engagements are already under way, although neither company has given a general availability date or commercial pricing, leaving the first deployments to establish whether semiconductor-specific modelling can produce a measurable reduction in closure time. If it merely generates more design alternatives for engineers to review, the productivity gain will be limited; if those alternatives arrive already filtered through valid EDA runs and retain context across long optimisation loops, the effect on advanced chip development could be considerably more substantial.
